PCH S0 Low Power
The PCH has many independent functions and I/O interfaces making power management a highly distributive task. The first level of power management is to control the independent resources and the best place to do that is in the controllers. The second level of power management is to control the shared resources, which requires communication amongst the users of the shared resources.
The PCH power states are a combination of first level and second level power management functions. The “deeper” the power state, meaning the lower power required, generally means that more resources are disabled.
PCH S0 Low Power State Definition
A high level description of the global PCH low power states are described in below table. This table does not discuss the conditions to enter into these states, only the summary of the PCH power actions that are taken. These states are also not rigid definitions of actual HW states meaning that there are not specific flows to enter into LPx states. Most of the power management on the PCH is done autonomously by the I/O interface’s controller and is not globally controlled.
38.4 MHz Crystal Shutdown
When the CPU and system are in a power management state that can tolerate gating the 38.4 MHz crystal clock, this circuit can be powered down. This occurs when the processor enters C10 state, the PCH is in LP3 and all other consumers of the 38.4 MHz XTAL de-assert their clock request.
CPU_C10_GATE#
When asserted, CPU_C10_GATE# is the indication to the system that the processor is entering C10 and can handle the voltages on the VCCIO, VCCSTG and VCCPLL_OC rails being lowered to 0 V. When de-asserted, the VCCIO and VCCSTG rails must ramp back up to their operational voltage levels. The power good indicators for these rails must still be asserted high when these rails are lowered to 0 V during CPU_C10_GATE# assertion and while these rails ramp back up to their operational levels after CPU_C10_GATE# de-assertion.
External Power Gating for HSIO/SRAM
External power gating for the HSIO and SRAM supply for additional power savings during connected standby states can be implemented by using EXT_PWR_GATE# to control a FET gating off the supply to PCH. The ramp time of the FET can be controlled via MODPHY_PM_CFG3.
- Directly Indicate HSIO and SRAM power rail are VCCMPHYGT_1P05 and VCCPRIM_GATED_1P05 .
- Directly Indicate EXT_PWR_GATE# and EXT_PWR_GATE2# are used for VCCMPHYGT_1P05 and VCCPRIM_GATED_1P05.
| Power rail | Control signal of FET switch |
| VCCMPHYGT_1P05 | EXT_PWR_GATE# |
| VCCPRIM_GATED_1P05 | EXT_PWR_GATE2# |
SLP_S0#
SLP_S0# is the indication to the system to enter the deterministic idle state (S0i3). This is a PCH hardware controlled output pin. This signal is defined as active low which means a 0 V indicates the deterministic idle state. Additional power saving steps such as VPCLVM may happen during this state.