Conditions for Checking the 38.4 MHz Clock

When there is a lack of activity, the PCH has the capability to stop the 38.4 MHz clock to conserve power. “Clock activity” is defined as any activity that would require the 38.4 MHz clock to be running.

Any of the following conditions will indicate that it is not okay to stop the 38.4 MHz clock:

• Cycles on eSPI
• SERIRQ activity

Conditions for Maintaining the 38.4 MHz Clock

eSPI or any other devices that wish to maintain the 38.4 MHz clock running will observe the CLKRUN# signal de-asserted, and then must re-assert if (drive it low) within 92 clocks.

• When the PCH has tri-stated the CLKRUN# signal after de-asserting it, the PCH then checks to see if the signal has been re-asserted (externally).
• After observing the CLKRUN# signal asserted for 1 clock, the PCH again starts asserting the signal.

Conditions for Stopping the 38.4 MHz Clock

• When there is a lack of activity (as defined above) for 29 to 30 clock cycles, the PCH de-asserts (drive high) CLKRUN# for 1 clock cycle and then tri-states the signal.
• If no device drives CLKRUN# low within 6 clock cycles after it has been de-asserted, the PCH will stop the 38.4 MHz clocks.

Conditions for Re-starting the 38.4 MHz Clock

• A peripheral asserts CLKRUN# to indicate that it needs the 38.4 MHz clock re-started.
• Observing the CLKRUN# signal asserted externally for 1 (free running) clock, the PCH again starts driving CLKRUN# asserted.

If an internal source requests the clock to be re-started, the PCH re-asserts CLKRUN#, then the PCH will start the 38.4 MHz clocks.