Microcode Update (Type 1) Rules

1. At least one Microcode Update (Type 1) Entry is required. There can be one or more Microcode Update Entries in the FIT.
2. BIOS may carry multiple Microcode Updates for multiple processors stepping support. Each Type 1 entry points to a distinct Microcode Update. Each Microcode Update includes a header followed by update data, which may be followed by Extension Signature Table. The address field in Type 1 entry points to the first byte of the Microcode Update Header.
3. Each Type 1 entry must point to an address that is accessible by the processor at reset (i.e., requires no chipset configuration to reach that address in the flash).
4. BIOS may have some empty Microcode Update slots. These slots are set aside by BIOS to store future Microcode Updates. It is suitable for a Type 1 entry to point to these empty slots if the first dword in the empty slot is 0xFFFF_​FFFF.
5. For a given processor stepping, multiple revisions of Microcode Updates may be released over time. The FIT can contain more than one Type 1 entry for a processor signature and Platform ID combination for recovery considerations. The processor will load the latest available microcode update by choosing the one that has higher revision ID. To comply with the microcode update requirement that BIOS must ensure the latest Microcode Update is loaded after a recovery.
6. Microcode updates pointed to by a type 1 entry must be aligned on a 16-byte address.
7. Microcode updates pointed to by a type 1 entry must not be compressed, encoded, or encrypted by the BIOS.
8. The C_​V bit in this entry should be clear to 0.
9. The Size field is not used. BIOS should clear this field to 0.