Intel® 700 Series Chipset Family On-Package Platform Controller Hub (PCH)
Datasheet, Volume 1 of 2
Supporting Raptor Lake - PX Platforms
ID
765585
Date
01/30/2023
Version
001
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Revision History
Introduction
PCH Controller Device IDs
Memory Mapping
System Management
High Precision Event Timer (HPET)
PCH Thermal Sensor
Power Delivery
Pin Straps
Electrical and Thermal Characteristics
8254 Timers
Audio Voice and Speech
Controller Link
Processor Sideband Signals
Digital Display Signals
Enhanced Serial Peripheral Interface (eSPI)
General Purpose Input and Output
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Gigabit Ethernet Controller
Integrated Sensor Hub (ISH)
PCH and System Clocks
PCI Express* (PCIe*)
Power Management
Real Time Clock (RTC)
System Management Interface and SMLink
Host System Management Bus (SMBus) Controller
Serial Peripheral Interface (SPI)
Touch Host Controller (THC)
Intel® Serial IO Generic SPI (GSPI) Controllers
Testability
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Universal Serial Bus (USB)
Connectivity Integrated (CNVi)
GPIO Serial Expander
Private Configuration Space Target Port ID
Miscellaneous Signals
Functional Description
Configurable GPIO Voltage
GPIO Buffer Impedance Compensation
Interrupt / IRQ via GPIO Requirement
Programmable Hardware Debouncer
Integrated Pull-ups and Pull-downs
SCI / SMI# and NMI
Timed GPIO
GPIO Blink (BK) and Serial Blink (SBK)
GPIO Ownership
Native Function and TERM Bit Setting
Functional Description
Interrupt Generation
PCI Express* Power Management
Dynamic Link Throttling
Port 8xh Decode
Separate Reference Clock with Independent SSC (SRIS)
Advanced Error Reporting
Single - Root I/O Virtualization (SR - IOV)
SERR# Generation
Hot - Plug
PCI Express* Lane Polarity Inversion
Precision Time Measurement (PTM)
Signal Description
Signal Name | Type | Description |
---|---|---|
PCH_JTAG_TCK | I/O | Test Clock Input (TCK): The test clock input provides the clock for the JTAG test logic. |
PCH_JTAG_TMS | I/OD | Test Mode Select (TMS): The signal is decoded by the Test Access Port (TAP) controller to control test operations. |
PCH_JTAG_TDI | I/OD | Test Data Input (TDI): Serial test instructions and data are received by the test logic at TDI. |
PCH_JTAG_TDO | I/OD | Test Data Output (TDO): TDO is the serial output for test instructions and data from the test logic defined in this standard. |
PCH_JTAGX | I/O | This pin is used to support merged debug port topologies. |
DBG_PMODE | O | ITP Power Mode Indicator. This signal is used to transmit processor and PCH power/reset information to the Debugger. |