Problem

Some Intel^® Processor Trace packets should be issued only between TIP.PGE (Target IP Packet.Packet Generation Enable) and TIP.PGD (Target IP Packet.Packet Generation Disable) packets. Due to this erratum, when a TIP.PGE packet is generated it may be preceded by a PSB+ (Packet Stream Boundary) that incorrectly includes FUP (Flow Update Packet) and MODE.Exec packets.

Implication

Due to this erratum, FUP and MODE.Exec may be generated unexpectedly.

Workaround

Decoders should ignore FUP and MODE.Exec packets that are not between TIP.PGE and TIP.PGD packets.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Execution of the FSAVE, FNSAVE, FSTENV, or FNSTENV instructions in real-address mode or virtual-8086 mode may save an incorrect value for the x87 FDP (FPU data pointer). This erratum does not apply if the last non-control x87 instruction had an unmasked exception.

Implication

Software operating in real-address mode or virtual-8086 mode that depends on the FDP value for non-control x87 instructions without unmasked exceptions may not operate properly. Intel^® has not observed this erratum in any commercially available software.

Workaround

None identified. Software should use the FDP value saved by the listed instructions only when the most recent non-control x87 instruction incurred an unmasked exception.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If a MOV SS or POP SS instruction generated a debug exception, and is not followed by an explicit write to the stack pointer (SP), the processor may fail to deliver the debug exception or, if it does, the DR6 register contents may not correctly reflect the causes of the debug exception.

Implication

Debugging software may fail to operate properly if a debug exception is lost or does not report complete information. Intel^® has not observed this erratum with any commercially available software.

Workaround

Software should explicitly write to the stack pointer immediately after executing MOV SS or POP SS.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Due to a rare microarchitectural condition, the second byte of a 2-byte CYC (Cycle Count) packet may be dropped without an OVF (Overflow) packet.

Implication

A trace decoder may signal a decode error due to the lost trace byte.

Workaround

None identified. A mitigation is available for this erratum. If a decoder encounters a multi-byte CYC packet where the second byte has bit 0 (Ext) set to 1, it should assume that 4095 cycles have passed since the prior CYC packet, and it should ignore the first byte of the CYC and treat the second byte as the start of a new packet.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

BMI1, BMI2, LZCNT, ADXC, and ADOX instructions may not generate an #UD fault, even though the respective CPUID feature flags do not enumerate them as supported instructions.

Implication

Software that relies on BMI1, BMI2, LZCNT, ADXC, and ADOX instructions to generate an #UD fault, may not work correctly.

Workaround

None identified. Software should check CPUID reported instructions availability and not rely on the #UD fault behavior.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On EPT violations, bit 4 of the Exit Qualification indicates whether the guest-physical address was writeable. When EPT is configured as supervisory shadow-stack (both bit 60 in EPT paging-structure leaf entry and bit 0 in EPT paging-structure entries are set), non-executable (bit 2 in EPT paging-structure entries is cleared), and non-writeable (bit 1 in EPT paging-structure entries is cleared) a VMExit due to a guest instruction fetch to a supervisory page may incorrectly set bit 4 of the Exit Qualification. Bits 3, 5, and 6 of the Exit Qualification are not impacted by this erratum.

Implication

Due to this erratum, bit 4 of the Exit Qualification may be incorrectly set. Intel^® has not observed this erratum on any commercially available software.

Workaround

EPT handlers processing an EPT violation due to an instruction fetch access on a present page should ignore the value of bit 4 of the Exit Qualification.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When operating in a virtualized environment, if shadow stack pages are mapped over an APIC page, the processor may generate spurious page faults on that shadow stack page whenever its linear to physical address translation is cached in the Translation Look-aside Buffer.

Implication

When this erratum occurs, the processor may generate a spurious page fault. Intel^® is not aware of any software that maps shadow stack pages over an APIC page.

Workaround

Software should avoid mapping shadow stack pages over the APIC page.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex micro-architectural conditions, when the processor receives a warm reset during BIOS initialization, the processor may hang with a machine check error reported in IA32_​MCi_​STATUS, with MCACOD (bits [15:0]) value of 0400H, and MSCOD (bits [31:16]) value of 0080H.

Implication

Due to this erratum, the processor may hang. Intel^® has only observed this erratum in a synthetic test environment.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On processors that support bus-lock detection (CPUID.(EAX=7, ECX=0).ECX[24]) and have it enabled (bit 2 in the IA32_​DEBUGCTL MSR (1D9h)), and employ an Extended Page Table (EPT) that is mapped to an uncacheable area (UC), and the EPT_​AD is enabled (bit 6 of the EPT Pointer is set), if the VMM performs an EPT modification on a predefined valid page while a virtual machine is running, the processor may hang.

Implication

Due to this erratum, the system may hang when bus-lock detection is enabled. Intel^® has not observed this erratum in any commercially available software.

Workaround

VMM should not map EPT tables to Uncacheable memory while using EPT_​AD.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If the processor root port receives an FetchAdd, Swap, or CAS TLP (an atomic operation) that is erroneous, it should generate a UR completion to the downstream requestor. If the TLP has an operand size greater than 4 bytes, the generated UR completion may report an operand size of 4 bytes, which may be interpreted as a malformed transaction.

Implication

When this erratum occurs, the processor may respond with a malformed transaction.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If the MSR_​MISC_​PWR_​MGMT.LOCK (MSR 1AAh, bit13 ) is set, a General Protection Exception (#GP) may not be signaled when MSR_​MISC_​PWR_​MGMT.ENABLE_​SDC (MSR 1AAh, bit 10) is cleared while IA32_​XSS.HDC (MSR DA0h, bit 13) is set and if IA32_​PKG_​HDC_​CTL.HDC_​PKG_​Enable (MSR DB0h, bit 0) was set at least once before.

Implication

Due to this erratum, MSR_​MISC_​PWR_​MGMT.ENABLE_​SDC may be cleared even though a #GP was not signaled.

Workaround

None identified. Software should not attempt to clear MSR_​MISC_​PWR_​MGMT.ENABLE_​SDC if the above #GP conditions are met.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the PCIe Link exits the L1.2 low-power link state, the link may fail to correctly train to L0.

Implication

Due to this erratum, a PCIe link may incur unexpected link recovery events or it may enter a Link_​Down state.

Workaround

It may be possible for a BIOS code change to workaround this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex microarchitectural conditions, the PCIe controller may transmit an incorrectly formed Transaction Layer Packet (TLP), which may fail CRC checks.

Implication

When this erratum occurs, the PCIe end point may record correctable errors resulting in either a NAK or link recovery. Intel^® has not observed any functional impact due to this erratum.

Workaround

None Identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex micro-architectural conditions, single step on branches (IA32_​DEBUGCTLMSR (Offset 1D9h, bit [1]) and also TF flag in EFLAGS register is set) in guest might be missed when VMM enables notification on VM Exit (IA32_​VMX_​PROCBASED_​CTLS2 MSR, Offset 48Bh, bit [31]) while the dirty access bit is not set for the code page (bit [6] in paging-structure entry).

Implication

When single step is enabled under the above condition, some single step branches may be missed. Intel^® has only observed this erratum in a synthetic test environment.

Workaround

When enabling single step on branches for debugging, software should first set the dirty bit of the code page.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If a #CP exception is triggered during a UIRET instruction execution, the error code on the stack may report NEAR-RET instruction (code 1) instead of FAR-RET instruction (code 2).

Implication

Due to this erratum, an incorrect #CP error code is logged when #CP is triggered during UIRET instruction.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

CPUID leaf 18H sub-leaf 04H EBX [31:16] reports 4 ways instead of 6 ways for the Load DTLB.

Implication

Due to this erratum, software that relies upon the number of ways in the load DTLB may operate sub optimally.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex micro-architectural conditions, when using Intel(r) Processor Trace (PT) with single range output larger than 4KB, disabling PT and then enabling PT using the TraceEn bit in IA32_​RTIT_​CTL MSR (MSR 570h, bit 0) may cause incorrect output values to be recorded.

Implication

Due to this erratum, a PT trace may contain incorrect values.

Workaround

None identified. Software should avoid using PT with single range output larger than 4KB.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

PERF_​METRICS_​AVAILABLE indication inside IA32_​PERF_​CAPABILITIES MSR (bit 15 in MSR 345h) reports whether MSR_​PERF_​METRICS is available. This indication may not be set unless BIOS disables E-cores in the system.

Implication

When this erratum occurs, the PERF_​METRICS are available even though IA32_​PERF_​CAPABILITIES.PERF_​METRICS_​AVAILABLE reports otherwise.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The OFFCORE_​REQUESTS_​OUTSTANDING.*DATA_​RD performance monitoring events (Event 20h; UMask 08h) counts the number of off-core outstanding data read transactions each cycle. Due to this erratum, an inaccurate count may be observed when Intel^® HyperThreading Technology is enabled and hardware prefetchers are enabled.

Implication

OFFCORE_​REQUESTS_​OUTSTANDING Performance Monitoring Events may be Inaccurate.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A #GP (global protection exception) that results from an instruction being longer than 15 bytes is prioritized and served before a #CP (Controlflow Protection exception) that was created due to a missing ENDBRx instruction at the target of an indirect branch.

Implication

Due to this erratum, during an indirect jump with ENDBRANCH tracking, if the processor lands on an illegal instruction with length longer than 15 bytes or that decodes to a CS limit, the processor may prioritize and deliver a #GP exception over the #CP exception.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex microarchitectural conditions, on systems with Control-flow Enforcement Technology (CET) enabled, hitting a predefined data breakpoint may not be reported in B0-B3 (bits 3:0) in the DR6 register if that breakpoint was set on the legacy code page bitmap.

Implication

Due to this erratum, software may not know which breakpoint triggered when setting breakpoints on the legacy code page bitmap.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When Intel^® Transactional Synchronization Extensions (TSX) is enabled, and there is an RTM (Restricted Transactional Memory))abort due to an INT1 or INT3 instruction, bit 5 of the RTM abort status (nested transaction execution) may not be set even if the RTM was nested.

Implication

Due to this erratum, software that manages RTM aborts cannot determine whether an abort is nested.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex micro-architectural conditions, an L2 prefetch MCE that should be reported with MCACOD 165h in IA32_​MC3_​STATUS MSR (MSR 40dh, bits [15:0]) may be reported with an MCACOD of 101h.

Implication

Due to this erratum, the reported MCACOD for this MCE may be incorrect.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

In 32-bit mode, a call instruction wrapping around the 32-bit address should save a return address near the bottom of the address space (low address) around address zero. Under complex micro-architectural conditions, a return instruction following such a call may return to the next sequential address instead (high address).

Implication

Due to this erratum, In 32-bit mode a return following a call instruction that wraps around the 32-bit address boundary may return to the next sequential IP without wrapping around the address, possibly resulting in a #PF. Intel^® has not observed this behavior on any commercially available software.

Workaround

Software should not place call instructions in addresses that wrap around the 32-bit address space in 32-bit mode.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If VM entry clears Intel^® PT (Intel^® Processor Trace) IA32_​RTIT_​CTL.TraceEn (MSR 570H, bit 0) while PacketEn is 1 then a FUP (Flow Update Packet) may precede the TIP.PGD (Target IP Packet, Packet Generation Disable). VM entry can clear TraceEn if the VM-entry MSR-load area includes an entry for the IA32_​RTIT_​CTL MSR.

Implication

When this erratum occurs, an unexpected FUP may be generated that creates the appearance of an asynchronous event taking place immediately before or during the VM entry.

Workaround

The Intel^® PT trace decoder may opt to ignore any FUP whose IP matches that of a VM entry instruction.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

An invalid instruction opcode that runs into another exception before fetching all instruction bytes (e.g. a #GP due to the instruction being longer than 15 bytes or a CS limit violation) may signal a #UD despite not fetching all instruction bytes under some microarchitectural conditions.

Implication

Due to this erratum, a #UD exception may be serviced before other exceptions. This does not occur for valid instructions. Intel^® has only observed this erratum in a synthetic test environment.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

An instruction breakpoint should have the highest priority and needs to be serviced before any other exception. In case an instruction breakpoint is marked on an illegal instruction longer than 15 bytes that starts in bytes 0-16 of a 32B-aligned chunk, and that instruction does not complete within the same 32B-aligned chunk, a General Protection Exception (#GP) on the same instruction may be serviced before the breakpoint exception.

Implication

Due to this erratum, an illegal instruction #GP exception may be serviced before an instruction breakpoint.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Instructions longer than 15 bytes should assert a General Protection Exception (#GP). For instructions longer than 15 bytes, a Page Fault Exception (#PF) from the subsequent page might be issued before the #GP exception in the following cases: 1. The GP instruction starts at byte 1 – 16 of the last 32B-aligned chunk of a page (starting the count at byte 0), and it is not a target of taken jump, and it does not complete within the same 32B-aligned chunk it started in. 2. The GP instruction starts at byte 17 of the last 32B-aligned chunk of a page.

Implication

Due to this erratum, an unexpected #PF exception might be serviced before a #GP exception.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A General Protection Exception (#GP) may not be signaled when writing non-zero values to the upper 32 bits of IA32_​L3_​QOS_​Mask_​15 MSR (Offset C9FH) even though they are defined as reserved bits.

Implication

Due to this erratum, a #GP may not be signaled when the upper bits of IA32_​L3_​QOS_​Mask_​15 are written with a non-zero value.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex micro-architectural conditions, the VMX-preemption timer may not generate a VM Exit if the VMX-preemption timer value is set to 1.

Implication

Due to this erratum, if the value configured to a value of 1, a VM exit may not occur.

Workaround

None identified. Software should avoid programming the VMX-preemption timer with a value of 1.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Setting MISC_​FEATURE_​CONTROL.DISABLE_​THREE_​STRIKE_​CNT (bit 11 in MSR 1A4h) does not prevent the three-strike counter from incrementing as documented; instead, it only prevents the signaling of the three-strike event once the counter has expired.

Implication

Due to this erratum, software may be able to see the three-strike logged in the MC3_​STATUS (MSR 40Dh, MCACOD = 400h [bits 15:0]) even when MISC_​FEATURE_​CONTROL.DISABLE_​THREE_​STRIKE_​CNT is set.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A VM Exit that occurs while the processor is serving a user interrupt in non-root mode should set the “asynchronous to instruction execution” bit in the Exit Qualification field in the Virtual Machine Control Structure (bit 16). However, if a VM Exit occurs during processing a user interrupt due to an APIC access, the bit may not be set.

Implication

Due to this erratum, the “asynchronous to instruction execution” bit may not be set if an APIC Access VM Exit occurs while the processor is serving a user interrupt. Intel^® has not observed this erratum with any commercially available software.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The processor's PCIe port (Bus 0, Device 1, Function 0/1/2 or Bus 0, Device 6, Function 0) does not transmit the Modified Compliance Test Pattern when in either 2.5 GT/S or 5.0 GT/s link speeds.

Implication

Due to this erratum, PCIe compliance testing may fail at 2.5 GT/S or 5.0 GT/s link speeds when enabling the Modified Compliance Test Pattern.

Workaround

None Identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

On USB 3.2 Gen 1x1 only capable ports, including ports configured as USB 3.2 Gen 1x1 by soft strap, the xHCI controller may send only 15 LFPS signals instead of a burst of 16 LFPS signals as specified by the USB 3.2 specification.

Implication

There are no known functional implications due to this erratum. LFPS handshake requires the receiver link partner to only detect 2 LFPS signals. This issue may impact the SuperSpeed compliance test case which checks for the 16 LFPS burst requirements: TD6.4, TD6.5, and TD7.31.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The act of one processor or system bus master writing data into a currently executing code segment of a second processor with the intent of having the second processor execute that data as code is called cross-modifying code (XMC). XMC that does not force the second processor to execute a synchronizing instruction prior to execution of the new code is called unsynchronized XMC.Software using unsynchronized XMC to modify the instruction byte stream of a processor can see unexpected or unpredictable execution behavior from the processor that is executing the modified code.

Implication

In this case the phrase "unexpected or unpredictable execution behavior" encompasses the generation of most of the exceptions listed in the Intel^® Architecture Software Developer's Manual Volume 3: System Programming Guide including a General Protection Fault (GPF) or other unexpected behaviors. In the event that unpredictable execution causes a GPF the application executing the unsynchronized XMC operation would be terminated by the operating system.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

GPU may hang when Async Compute is enabled

Implication

Due to this erratum, the GPU may hang when running high bandwidth GFx application such as benchmarks and/or games.

Workaround

None identified. The Async Compute feature may be disabled in a graphics driver update. See GFx Driver Revenue SV2 PR5 (101.3616 or later) and release notes.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The Type-C controller does not properly support Qword accesses to its MSI-X interrupt table which may lead to unexpected behavior.

Implication

When this erratum occurs, Qword reads do not return Unsupported Request and may not return correct data and Qword writes may lead to unexpected behavior. Intel^® has not observed this erratum to affect any commercially available software.

Workaround

Software should not utilize Qword access for the Type-C MSI-X table.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When the processor exits a package C6 or C8 power state, it may encounter a machine check exception (MCACOD=PCU internal Errors(0402h) / MSCOD=MESSAGE_​CHANNEL_​TIMEOUT (0409h) / PKGC_​EXIT_​SA_​FIVR_​UNLOBOTOMY_​TIMEOUT (0441h) / PKGC_​WATCHDOG_​HANG_​C2P2_​RSP (0462h)).

Implication

Due to this erratum the system may hang with machine check exception.

Workaround

It is possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex microarchitectural conditions Enhanced Intel^® SpeedStep transitions may lead to a system hang.

Implication

Due to this issue a system may hang with MCACODE GCACHEL2_​ERR_​ERR (010Ah).

Workaround

It is possible for a BIOS code change to workaround this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The processor accesses to TME exclude range may be encrypted but not decrypted if mapped to remap range.

Implication

Due to this erratum, the processor exclude range it may be encrypted but may but not decrypted if mapped to remap range.

Workaround

It may be possible for BIOS to workaround this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The PTM Propagation Delay Adaptation Interpretation B (PTMPDAIB) Bit is implemented at Configuration Space (CFG) Offset 158h instead of at 50h as documented in the PCI-SIG PTM Byte Ordering Adaptation Engineering Change Notice (ECN).

Implication

End Point Device (EPD) software that implements the PTM Byte Ordering Adaptation ECN may not be able to program their PTMPDAIB Bit correctly since it is located at a different register offset.

Workaround

None identified. To mitigate this issue, EPD software that implements the PTM Byte Ordering Adaptation ECN must access PTMPDAIB at CFG Offset 158h.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The INVLPG instruction should invalidate any global TLB entries for the specified linear address, regardless of PCID (Process-Context Identifier). Due to this erratum, INVLPG may fail to invalidate TLB entries for global pages with PCIDs different from the current PCID value. Note that, on affected processors, the CPU may not use global TLB entries with PCIDs different from the current PCID value. This erratum does not apply in VMX non-root operation. It applies only when PCIDs are enabled and either in VMX root operation or outside VMX operation.

Implication

When this erratum occurs, TLB entries may incorrectly remain valid, leading to unpredictable system behavior, including unexpected exceptions. This erratum does not apply to a guest operating system running in VMX non-root operation.

Workaround

It may be possible for BIOS to contain a workaround for this erratum. Alternatively, this can be worked around by software using INVPCID type 2 instead of INVLPG.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The processor may hang during a package C6 entry with a machine check (MCACOD = 0x0402, MCSCOD = 0x0485 or 0x046C).

Implication

Due to this erratum the system may hang.

Workaround

It is possible for BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex microarchitectural conditions, the branch predictor may produce an incorrect instruction pointer leading to unpredictable system behavior.

Implication

Due to this erratum, the system may exhibit unpredictable behavior.

Workaround

It may be possible for BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A non-zero value written to IA32_​MC2_​ADDR (40Ah) and IA32_​MC2_​MISC(40Bh) MSRs may be incorrectly cleared following a warm reset.

Implication

Due to this erratum, software that relies on the IA32_​MC2_​ADDR and IA32_​MC2_​MISC MSR values may not function correctly after a warm reset. Intel^® has not observed this erratum with any commercially available software.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The xHCI controller does not return the correct completion code for the Force Header Command as defined in the Section 4.6.16 of the eXtensible Host Controller Interface for Universal Serial Bus (xHCI) Requirements Specification Rev 1.2.

Implication

xHCI CV TD4.12 - Force Header Command Test may report an error. Intel^® has obtained a waiver for TD 4.12. The Force Header Command is only used by the USB-IF Command Verifier (xHCI CV) tool for device testing. There are no known functional failures due to this erratum.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

DDR5 Clock Jitter, as measured by jitter parameters Dj, Rj, and Tj (Dynamic/Random/Total jitter), may be beyond the JEDEC specification (JEDEC doc number JESD79-5B, Chapter 8.3) limits.

Implication

Due to this erratum Clock Jitter measurements may be out of spec. Intel has not observed any functional implications due to this erratum.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

IA32_​SPEC_​CTL (MSR 48h) bits IPRED_​DIS_​U (bit 3), IPRED_​DIS_​S (bit 4) and BHI_​DIS_​S (bit 10) may not function correctly after leaving a C6 or deeper sleep state.

Implication

Due to this erratum, software that relies upon these bit values may not behave as intended.

Workaround

It may be possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex micro-architectural conditions, the Time-Stamp Counter (TSC) may incorrectly report the time stamp to be less than the expected time stamp after exiting C6 power saving state.

Implication

Due to this erratum, systems that rely upon a monotonically increasing value reported by the TSC may exhibit unpredictable system behavior.

Workaround

It is possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex microarchitectural conditions, a read on one logical processor may not receive the most recently stored data by another logical processor.

Implication

Due to this erratum, unpredictable system behavior or a system hang may occur. Intel has only observed this behavior in a synthetic test environment. Intel has not observed this erratum with any commercially available system.

Workaround

It is possible for the BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The performance monitoring events IDQ.MS_​UOPS, IDQ.MS_​SWITCHES, and IDQ.MS_​CYCLES_​ANY (Event 79h, UMask 30h) may undercount MS_​UOPS that come from the Decode Stream Buffer (DSB).

Implication

Due to this erratum, performance monitoring counters may report counts lower than expected.

Workaround

None identified. Performance monitoring event UOPS_​RETIRED.MS may be used instead.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

The performance monitoring events TOPDOWN.BACKEND_​BOUND_​SLOTS (Event A4h, UMask 02h) and IDQ_​BUBBLES.* (Event 9Ch, UMask 01h) may not count when the processor is in the C0.2 power sub-state, which is entered via the TPAUSE or UWAIT instructions. This erratum also impacts the accuracy of MSR_​PERF_​METRICS fields Frontend Bound, Backend Bound, and Fetch Latency (MSR 329h, Bits [23:16], [31:24] and [55:48]).

Implication

Due to this erratum, these performance monitoring events and the fields in MSR_​PERF_​METRICS may be inaccurate.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When switching between Type-C Display Alt Mode and an Multi-Function Device (MFD) while the system is in S3/S4/S5, the Display may not enumerate.

Implication

When this erratum occurs the Display may be blank. A device unplug and re-plug may be necessary to recover the display.

Workaround

None identified.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When performing a warm reset as part of enabling of Intel^® Hyper-Threading, machine check banks may not be initialized correctly.

Implication

Due to this erratum, software that relies on initialized values in machine check banks may not behave as expected.

Workaround

None identified. Software or BIOS can avoid this erratum by performing cold reset when re-enabling Intel^® HT.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

A Packet Stream Boundary (PSB) packet should be generated for every PSBFreq number of trace output bytes. Due to this erratum, PSB packets may be generated only after as many as four times that number of output bytes have been generated.

Implication

Due to this erratum, trace decoder software may see fewer PSB packets than expected. This may lead to the trace decoder software needing to search further to find a starting point to decode or, when used in circular mode, being unable to decode the trace due to lacking any PSB packets.

Workaround

None identified. Software can request more frequent PSB packets by programming PSBFreq (bits[27:24]) of IA32_​RTIT_​CTL MSR (570H) to a value 1/4 of the desired value.

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

When a Processor Trace MODE.EXEC packet is generated due to a change in RFLAGS.IF (interrupt flag) or the CS.L or CS.D bits, the processor may not generate a CYC packet before generating the MODE.EXEC packet.

Implication

Due to this erratum, trace decoder software may not be able to precisely determine when mode changes that involve changing the interrupt flag or the application’s default operand size happened.

Workaround

None identified

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

If software disables the APIC by clearing APIC global enable flag (bit 11) in IA32_​APIC_​BASE (MSR 1Bh) while an interrupt is being delivered, the system may hang with a machine check exception reported in IA32_​​MCi_​​STATUS, with MCACOD (bits [15:0]) value of 0400H, and MSCOD (bits [31:16]) value of 0080H.

Implication

Due to this erratum, the system may hang. Intel has not observed this erratum in any commercial available software.

Workaround

None identified

Status

For the steppings affected, refer to the Summary Table of Changes.

Problem

Under complex microarchitectural conditions, a cache line split load may return incorrect data.

Implication

Due to this erratum, split loads may return incorrect data, which may lead to unpredictable system behavior. Intel has only observed this erratum in a synthetic test environment.

Workaround

It may be possible for BIOS to contain a workaround for this erratum.

Status

For the steppings affected, refer to the Summary Table of Changes.