Identification Information

Processor line naming conventions in this document:

• S, H, P, HX, and U Processor Line when referring to 13th Generation Intel^® Core™
• S Refresh, HX Refresh Processor when referring to Intel^® Core™ 14th Generation
• U Refresh Processor when referring to Intel^® Core™ Processor ("Series 1") and ("Series 2")
• H Refresh Processor when referring to Intel^® Core™ Processor ("Series 2")
• E Processor when referring to Intel^® Xeon^® E 2400 Processor
• E Refresh Processor when referring to Intel^® Xeon^® 6300 Processor

Component Identification via Programming Interface

The processor stepping is identified by the following register contents:

Table 2-1. Processor Lines Component Identification

• 1. The Extended Family, Bits [27:20] are used in conjunction with the Family Code, specified in Bits[11:8], to indicate whether the processor belongs to the Celeron^®, Pentium^®, or Intel^® Core™ processor family.
  2. The Extended Model, Bits [19:16] in conjunction with the Model Number, specified in Bits [7:4], are used to identify the model of the processor within the processor’s family.
  3. The Family Code corresponds to Bits [11:8] of the EDX register after RESET, Bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan.
  4. The Model Number corresponds to Bits [7:4] of the EDX register after RESET, Bits [7:4] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan.
  5. The Stepping ID in Bits [3:0] indicates the revision number of that model. Refer table above for the processor stepping ID number in the CPUID information.
  6. When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended Family, Extended Model, Processor Type, Family Code, Model Number and Stepping ID value in the EAX register. The EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register.

Component Marking Information

Figure 2-1. Processor Based on S/S-Refresh/E/E Refresh Processor Lines Chip Package LGA Top-Side Markings

Pin Count: 1700 Package Size (width x height): 37.5mm x 45mm

Production (SSPEC):

• SN345
• G1L1: SPARK (Intel logo)
• G2L1: TRADEMARK BRAND
• G3L1: PROCESSOR NUMBER
• G4L1: SSPEC
• G5L1: FPO_​{EX}
Note:“1” is used to extract the unit visual ID (2D ID).
“2” is Pin 1 indicator on IHS.

Figure 2-2. Processor Based on H/H-Refresh/P Processor Line Chip Package LGA Top-Side Markings



Pin Count: 1744 Package Size (width x height): 50mm x 25mm

Production (SSPEC):

• SN345
• G1L1: SPARK (Intel logo)
• G1L2: FPO
• G1L3: SSPEC
• G2L1: {ex}
Note:“1” is used to extract the unit visual ID (2D ID).

Figure 2-3. Processor Based on HX/HX-Refresh Processor Line Chip Package LGA Top-Side Markings



Pin Count: 1964 Package Size “(width x height)”: 37.5mm x 45mm

Production (SSPEC):

• SN345
• G1L1: SPARK (Intel logo)
• G2L1: FPO
• G3L1: SSPEC
• G4L1: {eX}
Note:“1” is used to extract the unit visual ID (2D ID).

Figure 2-4. Processor Based on U/U-Refresh Processor Line Chip Package LGA Top-Side Markings



Pin Count: 1744 Package Size (width x height): 50mm x 25mm

Production (SSPEC):

• SN345
• G1L1: SPARK (Intel logo)
• G2L1: FPO
• G3L1: SSPEC
• G4L1: {eX}Note:“1” is used to extract the unit visual ID (2D ID).