31:19

0h

RO

Reserved

18

0h

RW/1C/V

Wake Alarm Device Timer Status (WADT_​STS)

This bit is set whenever the any of the wake alarm device timers signal a timer expiration.

17:16

0h

RO

Reserved

15

0h

RW/1C/V

GPIO Tier2 SCI Status (GPIO_​TIER2_​SCI_​STS)

This bit is a logical OR of sci_​wake from tier 2 GPIO's.

14

0h

RW/1C/V

eSPI SCI Status (ESPI_​SCI_​STS)

This bit will be set when an agent attached to eSPI is requesting an SCI.

Note: This source is not able to cause a wake event.

13

0h

RW/1C/V

Power Management Event Bus 0 Status (PME_​B0_​STS)

This bit will be set to 1 by the Intel PCH when any internal device with PCI Power Management capabilities on bus 0 asserts the equivalent of the PME# signal. Additionally, if the PME_​B0_​EN and SCI_​EN bits are set, and the system is in an S0 state, then the setting of the PME_​B0_​STS bit will generate an SCI (or SMI# if SCI_​EN is not set). If the PME_​B0_​EN bit is set, and the system is in an S1-S4 state (or S5 state due to SLP_​TYP and SLP_​EN), then the setting of the PME_​B0_​STS bit will generate a wake event. If the system is in an S5 state due to power button override, then the PME_​B0_​STS bit will not cause a wake event or SCI. This bit is cleared by a software write of '1'.

Internal devices which can set this bit:

- Integrated LAN

- HD Audio/Audio DSP

- SATA

- EHCI ('USB2')

- XHCI ('USB3')

- ME Maskable Host Wake

12

0h

RW/1C/V

ME SCI Status (ME_​SCI_​STS)

This bit will be set when ME is requesting an SCI. Software must clear the ME source of the SCI before clearing this bit.

Note: This source is not able to cause a wake event.

11

0h

RW/1C/V

Power Management Event Status (PME_​STS)

This bit will be set to 1 by hardware when the PME# signal goes active. Additionally, if the PME_​EN and SCI_​EN bits are set, and system is in an S0 state, then the setting of the PME_​STS bit will generate an SCI (or SMI# if SCI_​EN is not set). If the PME_​EN bit is set, and the system is in an S1-S4 state (or S5 state due to SLP_​TYP and SLP_​EN), then the setting of the PME_​STS bit will generate a wake event. If the system is in an S5 state due to power button override, then PME_​STS will not cause a wake event or SCI. This bit is cleared by writing a 1 to this bit position.

10

0h

RW/1C/V

Battery Low Status (BATLOW_​STS)

In Mobile Mode this bit will be set to 1 by hardware when the BATLOW# signal goes low. Software clears the bit by writing a 1 to the bit position. In Desktop Mode, this bit will be treated as Reserved.

9

0h

RW/1C/V

PCI Express Status (PCI_​EXP_​STS)

This bit will be set to 1 by hardware to indicate that:

The PME event message was received on one or more of the PCI-Express Ports

An Assert PMEGPE message received from the Compute Tile

Note: The PCI WAKE# pin and the PCI-Express Beacons have no impact on this bit.

Software attempts to clear this bit by writing a 1 to this bit position. If the PCI_​EXP_​STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared.

If the bit is not cleared and the corresponding PCI_​EXP_​EN bit is set, the leveltriggered SCI will remain active.

8

0h

RO

Reserved

7

0h

RW/1C/V

SMBus Wake Status (SMB_​WAK_​STS)

This bit is set to 1 by the hardware to indicate that the wake event was caused by the SMBus logic. This could be due to either the SMBus slave unit receiving a message or the SMBALERT# signal going active.[BR]NOTES:[BR]1. The SMBus controller will independently cause an SMI# so this bit does not need to do so (unlike the other bits in this register).[BR]2. This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the system is in the S0 state. Therefore, to avoid an instant wake on subsequent transitions to sleep states, software must clear this bit after each reception of the Wake/SMI# command or just prior to entering the sleep state.[BR]3. The SMBALERT_​STS bit (D31:F3:I/O Offset 00h:bit 5) should be cleared by software before clearing this bit.[BR]This bit is reset by RSMRST# assertion.

6

0h

RW/1C/V

TCOSCI Status (TCOSCI_​STS)

This bit will be set to 1 by hardware when the TCO logic or Thermal Sensor logic causes an SCI. This bit can be reset by writing a one to this bit position.

5

0h

RO

Reserved

4

0h

RW/1C/V

Thermal SCI Status (THERM_​SCI_​STS)

This bit will be set to 1 by hardware when the firmware sets the DRV_​THERM_​SMI_​SCI_​STS.DRV_​SCI_​STS. This bit can be cleared by writing a one to this bit position.

3

0h

RW/1C/V

eSPI Unconditional Wake Status (ESPIUWAK_​STS)

This bit is set to 1 by hardware upon reception of an unconditional wake message from eSPI

2

0h

RW/1C/V

Software GPE Status (SWGPE_​STS)

The SWGPE_​CTRL bit (bit 1 of GPE_​CTRL reg) acts as a level input to this bit.[BR]This bit is reset by RSMRST# assertion.

1

0h

RW/1C/V

Hot Plug Status (HOT_​PLUG_​STS)

This bit is set to 1 by hardware when a PCI-Express hotplug event occurs. This will cause an SCI if the HOT_​PLUG_​EN and SCI_​EN bits are set. This bit is cleared by writing a 1 to this bit position. The following events cause this bit to set

- Assert GPE message received from any of the PCIE ports in the SoC Tile[BR]
- Assert HPGPE message received from any of the PCIE ports in the SoC Tile[BR]
- Assert GPE message received downstream from the Compute Tile[BR]
- Assert HPGPE message received downstream from the compute tile.[BR]This bit is reset by RSMRST# assertion.

0

0h

RO

Reserved