Last TSC Alarm Value[63:32] (TSC_ALARM_HI) – Offset 1914 - 001 - ID:819325 | Intel® Core™ Ultra Processors for Edge (PS Series) IOE-P I/O Registers

Last TSC Alarm Value[63:32] (TSC_ALARM_HI) – Offset 1914

Intel® Core™ Ultra Processors for Edge (PS Series) IOE-P I/O Registers

ID	Date	Version	Classification
819325	04/02/2024	001	Public

Document Table of Contents

Introduction P2SB PCI Configuration PCI Express* (PCIe*) Configuration (D1:F0) PCI Express* (PCIe*) Configuration (D6:F1) PCI Express* (PCIe*) Configuration (D6:F2) PMC I/O PMC MMIO PMC PCI Configuration SSRAM PCI Configuration USB xHCI MMIO USB xHCI PCI Configuration

Introduction

P2SB PCI Configuration

P2SB PCI Configuration PCI Subsystem Identifiers (PCIHSS) PCI Capabilities Pointer (CAPPTR) PCI Express Capability List Register (EXPCAPLST) PCI Express Capabilities Register (EXPCAP) Device Capabilities Register (DEVCAP) Device Control Register (DEVCTL) Device Status Register (DEVSTS) Link Capabilities Register (LNKCAP) Link Control Register (LNKCTL) Link Status Register (LNKSTS) Unsupported Request Error Status (URES) Unsupported Request Error Control (UREC) Sideband Register Posted 0 (SBREGPOSTED0) Sideband Register Posted 1 (SBREGPOSTED1) Sideband Register Posted 2 (SBREGPOSTED2) Sideband Register Posted 3 (SBREGPOSTED3) Sideband Register Posted 4 (SBREGPOSTED4) Sideband Register Posted 5 (SBREGPOSTED5) Sideband Register Posted 6 (SBREGPOSTED6) Sideband Register Posted 7 (SBREGPOSTED7) SAI Policy Control (SAIPOLCTRL0) SAI Policy Control (SAIPOLCTRL1) SAI Policy Write Access Control (SAIPOLWAC0) SAI Policy write Access Control (SAIPOLWAC1) SAI Policy Read Access Control (SAIPOLRAC0) SAI Policy Read Access Control (SAIPOLRAC1) Group 1 SAI Policy Control (G1SAIPOLCTRL0) Group 1 SAI Policy Control (G1SAIPOLCTRL1) Group 1 SAI Policy Write Access Control (G1SAIPOLWAC0) Group 1 SAI Policy write Access Control (G1SAIPOLWAC1) Group 1 SAI Policy Read Access Control (G1SAIPOLRAC0) Group 1 SAI Policy Read Access Control (G1SAIPOLRAC1)

PCI Subsystem Identifiers (PCIHSS)

PCI Capabilities Pointer (CAPPTR)

PCI Express Capability List Register (EXPCAPLST)

PCI Express Capabilities Register (EXPCAP)

Device Capabilities Register (DEVCAP)

Device Control Register (DEVCTL)

Device Status Register (DEVSTS)

Link Capabilities Register (LNKCAP)

Link Control Register (LNKCTL)

Link Status Register (LNKSTS)

Unsupported Request Error Status (URES)

Unsupported Request Error Control (UREC)

Sideband Register Posted 0 (SBREGPOSTED0)

Sideband Register Posted 1 (SBREGPOSTED1)

Sideband Register Posted 2 (SBREGPOSTED2)

Sideband Register Posted 3 (SBREGPOSTED3)

Sideband Register Posted 4 (SBREGPOSTED4)

Sideband Register Posted 5 (SBREGPOSTED5)

Sideband Register Posted 6 (SBREGPOSTED6)

Sideband Register Posted 7 (SBREGPOSTED7)

SAI Policy Control (SAIPOLCTRL0)

SAI Policy Control (SAIPOLCTRL1)

SAI Policy Write Access Control (SAIPOLWAC0)

SAI Policy write Access Control (SAIPOLWAC1)

SAI Policy Read Access Control (SAIPOLRAC0)

SAI Policy Read Access Control (SAIPOLRAC1)

Group 1 SAI Policy Control (G1SAIPOLCTRL0)

Group 1 SAI Policy Control (G1SAIPOLCTRL1)

Group 1 SAI Policy Write Access Control (G1SAIPOLWAC0)

Group 1 SAI Policy write Access Control (G1SAIPOLWAC1)

Group 1 SAI Policy Read Access Control (G1SAIPOLRAC0)

Group 1 SAI Policy Read Access Control (G1SAIPOLRAC1)

PCI Express* (PCIe*) Configuration (D1:F0)

PCIE Identifiers (ID)

Device Command (CMD)

Primary Status (PSTS)

Revision ID (RID_CC)

Cache Line Size (CLS)

Primary Latency Timer (PLT)

Header Type (HTYPE)

Base Address Register 0 (BAR0)

Base Address Register 1 (BAR1)

Bus Numbers (BNUM_SLT)

I/O Base And Limit (IOBL)

Secondary Status (SSTS)

Memory Base And Limit (MBL)

Prefetchable Memory Base And Limit (PMBL)

Prefetchable Memory Base Upper 32 Bits (PMBU32)

Prefetchable Memory Limit Upper 32 Bits (PMLU32)

Capabilities List Pointer (CAPP)

Interrupt Information Byte 0 (INTRB0)

Interrupt Information Byte 1 (INTRB1)

Bridge Control (BCTRL)

Capabilities List (CLIST)

PCI Express Capabilities (XCAP)

Device Capabilities (DCAP)

Device Control (DCTL)

Device Status (DSTS)

Link Capabilities (LCAP)

Link Control (LCTL)

Link Status (LSTS)

Slot Capabilities (SLCAP)

Slot Control (SLCTL)

Slot Status (SLSTS)

Root Control (RCTL)

Root Capabilities (ROOTCAP)

Root Status (RSTS)

Device Capabilities 2 (DCAP2)

Device Control 2 (DCTL2)

Device Status 2 (DSTS2)

Link Capabilities 2 (LCAP2)

Link Control 2 (LCTL2)

Link Status 2 (LSTS2)

Slot Capabilities 2 (SLCAP2)

Slot Control 2 (SLCTL2)

Slot Status 2 (SLSTS2)

Message Signaled Interrupt Identifiers (MID)

Message Signaled Interrupt Message (MC)

Message Signaled Interrupt Message Address (MA)

Message Signaled Interrupt Message Upper Address (MUA)

Message Signaled Interrupt Message Data (MD)

Subsystem Vendor Capability (SVCAP)

Subsystem Vendor IDs (SVID)

Power Management Capability (PMCAP)

PCI Power Management Capabilities (PMC)

PCI Power Management Control (PMCS)

Advanced Error Extended (AECH)

Uncorrectable Error Status (UES)

Uncorrectable Error Mask (UEM)

Uncorrectable Error Severity (UEV)

Correctable Error Status (CES)

Correctable Error Mask (CEM)

Advanced Error Capabilities And Control (AECC)

Root Error Command (REC)

Root Error Status (RES)

Error Source Identification (ESID)

TLP Prefix Log 1 (TLPPL1)

TLP Prefix Log 2 (TLPPL2)

TLP Prefix Log 3 (TLPPL3)

TLP Prefix Log 4 (TLPPL4)

PTM Extended Capability Header (PTMECH)

PTM Capability Register (PTMCAPR)

PTM Control Register (PTMCTLR)

L1 Sub-States Extended Capability Header (L1SECH)

L1 Sub-States Capabilities (L1SCAP)

L1 Sub-States Control 1 (L1SCTL1)

L1 Sub-States Control 2 (L1SCTL2)

ACS Extended Capability Header (ACSECH)

ACS Capability Register (ACSCAPR)

ACS Control Register (ACSCTLR)

Port VC Capability Register 1 (PVCCR1)

Port VC Capability 2 (PVCC2)

Port VC Control (PVCC)

Port VC Status (PVCS)

Virtual Channel 0 Resource Capability (V0VCRC)

Virtual Channel 0 Resource Control (V0CTL)

Virtual Channel 0 Resource Status (V0STS)

Virtual Channel 1 Resource Capability (V1VCRC)

Virtual Channel 1 Resource Control (V1CTL)

Virtual Channel 1 Resource Status (V1STS)

DPC Extended Capability Header (DPCECH)

DPC Capability Register (DPCCAPR)

DPC Control Register (DPCCTLR)

DPC Status Register (DPCSR)

DPC Error Source ID Register (DPCESIDR)

RP PIO Status Register (RPPIOSR)

RP PIO Mask Register (RPPIOMR)

RP PIO Severity Register (RPPIOVR)

RP PIO SysError Register (RPPIOSER)

RP PIO Exception Register (RPPIOER)

RP PIO Header Log DW1 Register (RPPIOHLR_DW1)

RP PIO Header Log DW2 Register (RPPIOHLR_DW2)

RP PIO Header Log DW3 Register (RPPIOHLR_DW3)

RP PIO Header Log DW4 Register (RPPIOHLR_DW4)

Secondary PCI Express Extended Capability Header (SPEECH)

Link Control 3 (LCTL3)

Lane Error Status (LES)

Lane 0 And Lane 1 Equalization Control (L01EC)

Lane 2 And Lane 3 Equalization Control (L23EC)

Lane 4 And Lane 5 Equalization Control (L45EC)

Lane 6 And Lane 7 Equalization Control (L67EC)

Lane 8 And Lane 9 Equalization Control (L89EC)

Lane 10 And Lane 11 Equalization Control (L1011EC)

Lane 12 And Lane 13 Equalization Control (L1213EC)

Lane 14 And Lane 15 Equalization Control (L1415EC)

Data Link Feature Extended Capability Header (DLFECH)

Data Link Feature Capabilities Register (DLFCAP)

Data Link Feature Status Register (DLFSTS)

Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH)

Physical Layer 16.0 GT/s Capability Register (PL16CAP)

Physical Layer 16.0 GT/s Control Register (PL16CTL)

Physical Layer 16.0 GT/s Status Register (PL16S)

Physical Layer 16.0 GT/s Local Data Parity Mismatch Status Register (PL16LDPMS)

Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS)

Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS)

Physical Layer 16.0 GT/s Extra Status Register (PL16ES)

Physical Layer 16.0 GT/s Lane 01 Equalization Control Register (PL16L01EC)

Physical Layer 16.0 GT/s Lane 23 Equalization Control Register (PL16L23EC)

Physical Layer 16.0 GT/s Lane 45 Equalization Control Register (PL16L45EC)

Physical Layer 16.0 GT/s Lane 67 Equalization Control Register (PL16L67EC)

Physical Layer 16.0 GT/s Lane 89 Equalization Control Register (PL16L89EC)

Physical Layer 16.0 GT/s Lane 1011 Equalization Control Register (PL16L1011EC)

Physical Layer 16.0 GT/s Lane 1213 Equalization Control Register (PL16L1213EC)

Physical Layer 16.0 GT/s Lane 1415 Equalization Control Register (PL16L1415EC)

Physical Layer 32.0 GT/s Extended Capability Header (G5ECH)

Physical Layer 32.0 GT/s Capability Register (G5CAP)

Physical Layer 32.0 GT/s Control Register (G5CTL)

Physical Layer 32.0 GT/s Status Register (G5STS)

Receiver Modified TS Data 1 Register (RCVDMODTSDATA1)

Receiver Modified TS Data 2 Register (RCVDMODTSDATA2)

Transmitted Modified TS Data 1 Register (TRNSMODTSDATA1)

Transmitted Modified TS Data 2 Register (TRNSMODTSDATA2)

32.0 GT/s Lane 0123 Equalization Control Register (G5LANEEQCTL_0)

32.0 GT/s Lane 4567 Equalization Control Register (G5LANEEQCTL_4)

32.0 GT/s Lane 891011 Equalization Control Register (G5LANEEQCTL_8)

32.0 GT/s Lane 12131415 Equalization Control Register (G5LANEEQCTL_12)

Alternate Protocol Extended Capability Header (APEC)

Alternate Protocol Capabilities Register (APCAPR)

Alternate Protocol Control Register (APCTRLR)

Alternate Protocol Data 1 Register (APD1R)

Alternate Protocol Data 2 Register (APD2R)

Alternate Protocol Selective Enable Mask Register (APSEMR)

Multicast Extended Capability Header (MCECH)

Multicast Extended Capability Register (MCAPR)

Multicast Control Register (MCCTLR)

Multicast Base Address Register 1 (MCBADRR1)

Multicast Base Address Register 2 (MCBADRR2)

Multicast Receive Register (MCRR)

Multicast Block All Register (MCBAR)

Multicast Block Untranslated Register (MCBUR)

Multicast Overlay BAR 1 (MCOB1)

Multicast Overlay BAR 2 (MCOB2)

VNN Removal Control (VNNREMCTL)

VNN Removal Save And Restore Hardware Contexts 1 (VNNRSNRC1)

Physical Layer 16.0 GT/s Margining Extended Capability Header (PL16MECH)

Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status Byte 0 & 1 (PL16MPCPSB01)

Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status Byte 2 & 3 (PL16MPCPSB23)

Physical Layer 16.0 GT/s Lane0 Margin Control and Status Register (PL16L0MCS)

Physical Layer 16.0 GT/s Lane1 Margin Control and Status Register (PL16L1MCS)

Physical Layer 16.0 GT/s Lane2 Margin Control and Status Register (PL16L2MCS)

Physical Layer 16.0 GT/s Lane3 Margin Control and Status Register (PL16L3MCS)

Physical Layer 16.0 GT/s Lane4 Margin Control and Status Register (PL16L4MCS)

Physical Layer 16.0 GT/s Lane5 Margin Control and Status Register (PL16L5MCS)

Physical Layer 16.0 GT/s Lane6 Margin Control and Status Register (PL16L6MCS)

Physical Layer 16.0 GT/s Lane7 Margin Control and Status Register (PL16L7MCS)

Physical Layer 16.0 GT/s Lane8 Margin Control and Status Register (PL16L8MCS)

Physical Layer 16.0 GT/s Lane9 Margin Control and Status Register (PL16L9MCS)

Physical Layer 16.0 GT/s Lane10 Margin Control and Status Register (PL16L10MCS)

Physical Layer 16.0 GT/s Lane11 Margin Control and Status Register (PL16L11MCS)

Physical Layer 16.0 GT/s Lane12 Margin Control and Status Register (PL16L12MCS)

Physical Layer 16.0 GT/s Lane13 Margin Control and Status Register (PL16L13MCS)

Physical Layer 16.0 GT/s Lane14 Margin Control and Status Register (PL16L14MCS)

Physical Layer 16.0 GT/s Lane15 Margin Control and Status Register (PL16L15MCS)

PCI Express* (PCIe*) Configuration (D6:F1)

PCIE Identifiers (ID)

Device Command (CMD)

Primary Status (PSTS)

Revision ID (RID_CC)

Cache Line Size (CLS)

Primary Latency Timer (PLT)

Header Type (HTYPE)

Base Address Register 0 (BAR0)

Base Address Register 1 (BAR1)

Bus Numbers (BNUM_SLT)

I/O Base And Limit (IOBL)

Secondary Status (SSTS)

Memory Base And Limit (MBL)

Prefetchable Memory Base And Limit (PMBL)

Prefetchable Memory Base Upper 32 Bits (PMBU32)

Prefetchable Memory Limit Upper 32 Bits (PMLU32)

Capabilities List Pointer (CAPP)

Interrupt Information Byte 0 (INTRB0)

Interrupt Information Byte 1 (INTRB1)

Bridge Control (BCTRL)

Capabilities List (CLIST)

PCI Express Capabilities (XCAP)

Device Capabilities (DCAP)

Device Control (DCTL)

Device Status (DSTS)

Link Capabilities (LCAP)

Link Control (LCTL)

Link Status (LSTS)

Slot Capabilities (SLCAP)

Slot Control (SLCTL)

Slot Status (SLSTS)

Root Control (RCTL)

Root Capabilities (ROOTCAP)

Root Status (RSTS)

Device Capabilities 2 (DCAP2)

Device Control 2 (DCTL2)

Device Status 2 (DSTS2)

Link Capabilities 2 (LCAP2)

Link Control 2 (LCTL2)

Link Status 2 (LSTS2)

Slot Capabilities 2 (SLCAP2)

Slot Control 2 (SLCTL2)

Slot Status 2 (SLSTS2)

Message Signaled Interrupt Identifiers (MID)

Message Signaled Interrupt Message (MC)

Message Signaled Interrupt Message Address (MA)

Message Signaled Interrupt Message Upper Address (MUA)

Message Signaled Interrupt Message Data (MD)

Subsystem Vendor Capability (SVCAP)

Subsystem Vendor IDs (SVID)

Power Management Capability (PMCAP)

PCI Power Management Capabilities (PMC)

PCI Power Management Control (PMCS)

Advanced Error Extended (AECH)

Uncorrectable Error Status (UES)

Uncorrectable Error Mask (UEM)

Uncorrectable Error Severity (UEV)

Correctable Error Status (CES)

Correctable Error Mask (CEM)

Advanced Error Capabilities And Control (AECC)

Root Error Command (REC)

Root Error Status (RES)

Error Source Identification (ESID)

TLP Prefix Log 1 (TLPPL1)

TLP Prefix Log 2 (TLPPL2)

TLP Prefix Log 3 (TLPPL3)

TLP Prefix Log 4 (TLPPL4)

PTM Extended Capability Header (PTMECH)

PTM Capability Register (PTMCAPR)

PTM Control Register (PTMCTLR)

L1 Sub-States Extended Capability Header (L1SECH)

L1 Sub-States Capabilities (L1SCAP)

L1 Sub-States Control 1 (L1SCTL1)

L1 Sub-States Control 2 (L1SCTL2)

ACS Extended Capability Header (ACSECH)

ACS Capability Register (ACSCAPR)

ACS Control Register (ACSCTLR)

Port VC Capability Register 1 (PVCCR1)

Port VC Capability 2 (PVCC2)

Port VC Control (PVCC)

Port VC Status (PVCS)

Virtual Channel 0 Resource Capability (V0VCRC)

Virtual Channel 0 Resource Control (V0CTL)

Virtual Channel 0 Resource Status (V0STS)

Virtual Channel 1 Resource Capability (V1VCRC)

Virtual Channel 1 Resource Control (V1CTL)

Virtual Channel 1 Resource Status (V1STS)

DPC Extended Capability Header (DPCECH)

DPC Capability Register (DPCCAPR)

DPC Control Register (DPCCTLR)

DPC Status Register (DPCSR)

DPC Error Source ID Register (DPCESIDR)

RP PIO Status Register (RPPIOSR)

RP PIO Mask Register (RPPIOMR)

RP PIO Severity Register (RPPIOVR)

RP PIO SysError Register (RPPIOSER)

RP PIO Exception Register (RPPIOER)

RP PIO Header Log DW1 Register (RPPIOHLR_DW1)

RP PIO Header Log DW2 Register (RPPIOHLR_DW2)

RP PIO Header Log DW3 Register (RPPIOHLR_DW3)

RP PIO Header Log DW4 Register (RPPIOHLR_DW4)

Secondary PCI Express Extended Capability Header (SPEECH)

Link Control 3 (LCTL3)

Lane Error Status (LES)

Lane 0 And Lane 1 Equalization Control (L01EC)

Lane 2 And Lane 3 Equalization Control (L23EC)

Lane 4 And Lane 5 Equalization Control (L45EC)

Lane 6 And Lane 7 Equalization Control (L67EC)

Lane 8 And Lane 9 Equalization Control (L89EC)

Lane 10 And Lane 11 Equalization Control (L1011EC)

Lane 12 And Lane 13 Equalization Control (L1213EC)

Lane 14 And Lane 15 Equalization Control (L1415EC)

Data Link Feature Extended Capability Header (DLFECH)

Data Link Feature Capabilities Register (DLFCAP)

Data Link Feature Status Register (DLFSTS)

Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH)

Physical Layer 16.0 GT/s Capability Register (PL16CAP)

Physical Layer 16.0 GT/s Control Register (PL16CTL)

Physical Layer 16.0 GT/s Status Register (PL16S)

Physical Layer 16.0 GT/s Local Data Parity Mismatch Status Register (PL16LDPMS)

Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS)

Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS)

Physical Layer 16.0 GT/s Extra Status Register (PL16ES)

Physical Layer 16.0 GT/s Lane 01 Equalization Control Register (PL16L01EC)

Physical Layer 16.0 GT/s Lane 23 Equalization Control Register (PL16L23EC)

Physical Layer 16.0 GT/s Lane 45 Equalization Control Register (PL16L45EC)

Physical Layer 16.0 GT/s Lane 67 Equalization Control Register (PL16L67EC)

Physical Layer 16.0 GT/s Lane 89 Equalization Control Register (PL16L89EC)

Physical Layer 16.0 GT/s Lane 1011 Equalization Control Register (PL16L1011EC)

Physical Layer 16.0 GT/s Lane 1213 Equalization Control Register (PL16L1213EC)

Physical Layer 16.0 GT/s Lane 1415 Equalization Control Register (PL16L1415EC)

Physical Layer 32.0 GT/s Extended Capability Header (G5ECH)

Physical Layer 32.0 GT/s Capability Register (G5CAP)

Physical Layer 32.0 GT/s Control Register (G5CTL)

Physical Layer 32.0 GT/s Status Register (G5STS)

Receiver Modified TS Data 1 Register (RCVDMODTSDATA1)

Receiver Modified TS Data 2 Register (RCVDMODTSDATA2)

Transmitted Modified TS Data 1 Register (TRNSMODTSDATA1)

Transmitted Modified TS Data 2 Register (TRNSMODTSDATA2)

32.0 GT/s Lane 0123 Equalization Control Register (G5LANEEQCTL_0)

32.0 GT/s Lane 4567 Equalization Control Register (G5LANEEQCTL_4)

32.0 GT/s Lane 891011 Equalization Control Register (G5LANEEQCTL_8)

32.0 GT/s Lane 12131415 Equalization Control Register (G5LANEEQCTL_12)

Alternate Protocol Extended Capability Header (APEC)

Alternate Protocol Capabilities Register (APCAPR)

Alternate Protocol Control Register (APCTRLR)

Alternate Protocol Data 1 Register (APD1R)

Alternate Protocol Data 2 Register (APD2R)

Alternate Protocol Selective Enable Mask Register (APSEMR)

Multicast Extended Capability Header (MCECH)

Multicast Extended Capability Register (MCAPR)

Multicast Control Register (MCCTLR)

Multicast Base Address Register 1 (MCBADRR1)

Multicast Base Address Register 2 (MCBADRR2)

Multicast Receive Register (MCRR)

Multicast Block All Register (MCBAR)

Multicast Block Untranslated Register (MCBUR)

Multicast Overlay BAR 1 (MCOB1)

Multicast Overlay BAR 2 (MCOB2)

VNN Removal Control (VNNREMCTL)

VNN Removal Save And Restore Hardware Contexts 1 (VNNRSNRC1)

Physical Layer 16.0 GT/s Margining Extended Capability Header (PL16MECH)

Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status Byte 0 & 1 (PL16MPCPSB01)

Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status Byte 2 & 3 (PL16MPCPSB23)

Physical Layer 16.0 GT/s Lane0 Margin Control and Status Register (PL16L0MCS)

Physical Layer 16.0 GT/s Lane1 Margin Control and Status Register (PL16L1MCS)

Physical Layer 16.0 GT/s Lane2 Margin Control and Status Register (PL16L2MCS)

Physical Layer 16.0 GT/s Lane3 Margin Control and Status Register (PL16L3MCS)

Physical Layer 16.0 GT/s Lane4 Margin Control and Status Register (PL16L4MCS)

Physical Layer 16.0 GT/s Lane5 Margin Control and Status Register (PL16L5MCS)

Physical Layer 16.0 GT/s Lane6 Margin Control and Status Register (PL16L6MCS)

Physical Layer 16.0 GT/s Lane7 Margin Control and Status Register (PL16L7MCS)

Physical Layer 16.0 GT/s Lane8 Margin Control and Status Register (PL16L8MCS)

Physical Layer 16.0 GT/s Lane9 Margin Control and Status Register (PL16L9MCS)

Physical Layer 16.0 GT/s Lane10 Margin Control and Status Register (PL16L10MCS)

Physical Layer 16.0 GT/s Lane11 Margin Control and Status Register (PL16L11MCS)

Physical Layer 16.0 GT/s Lane12 Margin Control and Status Register (PL16L12MCS)

Physical Layer 16.0 GT/s Lane13 Margin Control and Status Register (PL16L13MCS)

Physical Layer 16.0 GT/s Lane14 Margin Control and Status Register (PL16L14MCS)

Physical Layer 16.0 GT/s Lane15 Margin Control and Status Register (PL16L15MCS)

PCI Express* (PCIe*) Configuration (D6:F2)

PCIE Identifiers (ID)

Device Command (CMD)

Primary Status (PSTS)

Revision ID (RID_CC)

Cache Line Size (CLS)

Primary Latency Timer (PLT)

Header Type (HTYPE)

Base Address Register 0 (BAR0)

Base Address Register 1 (BAR1)

Bus Numbers (BNUM_SLT)

I/O Base And Limit (IOBL)

Secondary Status (SSTS)

Memory Base And Limit (MBL)

Prefetchable Memory Base And Limit (PMBL)

Prefetchable Memory Base Upper 32 Bits (PMBU32)

Prefetchable Memory Limit Upper 32 Bits (PMLU32)

Capabilities List Pointer (CAPP)

Interrupt Information Byte 0 (INTRB0)

Interrupt Information Byte 1 (INTRB1)

Bridge Control (BCTRL)

Capabilities List (CLIST)

PCI Express Capabilities (XCAP)

Device Capabilities (DCAP)

Device Control (DCTL)

Device Status (DSTS)

Link Capabilities (LCAP)

Link Control (LCTL)

Link Status (LSTS)

Slot Capabilities (SLCAP)

Slot Control (SLCTL)

Slot Status (SLSTS)

Root Control (RCTL)

Root Capabilities (ROOTCAP)

Root Status (RSTS)

Device Capabilities 2 (DCAP2)

Device Control 2 (DCTL2)

Device Status 2 (DSTS2)

Link Capabilities 2 (LCAP2)

Link Control 2 (LCTL2)

Link Status 2 (LSTS2)

Slot Capabilities 2 (SLCAP2)

Slot Control 2 (SLCTL2)

Slot Status 2 (SLSTS2)

Message Signaled Interrupt Identifiers (MID)

Message Signaled Interrupt Message (MC)

Message Signaled Interrupt Message Address (MA)

Message Signaled Interrupt Message Upper Address (MUA)

Message Signaled Interrupt Message Data (MD)

Subsystem Vendor Capability (SVCAP)

Subsystem Vendor IDs (SVID)

Power Management Capability (PMCAP)

PCI Power Management Capabilities (PMC)

PCI Power Management Control (PMCS)

Advanced Error Extended (AECH)

Uncorrectable Error Status (UES)

Uncorrectable Error Mask (UEM)

Uncorrectable Error Severity (UEV)

Correctable Error Status (CES)

Correctable Error Mask (CEM)

Advanced Error Capabilities And Control (AECC)

Root Error Command (REC)

Root Error Status (RES)

Error Source Identification (ESID)

TLP Prefix Log 1 (TLPPL1)

TLP Prefix Log 2 (TLPPL2)

TLP Prefix Log 3 (TLPPL3)

TLP Prefix Log 4 (TLPPL4)

PTM Extended Capability Header (PTMECH)

PTM Capability Register (PTMCAPR)

PTM Control Register (PTMCTLR)

L1 Sub-States Extended Capability Header (L1SECH)

L1 Sub-States Capabilities (L1SCAP)

L1 Sub-States Control 1 (L1SCTL1)

L1 Sub-States Control 2 (L1SCTL2)

ACS Extended Capability Header (ACSECH)

ACS Capability Register (ACSCAPR)

ACS Control Register (ACSCTLR)

Port VC Capability Register 1 (PVCCR1)

Port VC Capability 2 (PVCC2)

Port VC Control (PVCC)

Port VC Status (PVCS)

Virtual Channel 0 Resource Capability (V0VCRC)

Virtual Channel 0 Resource Control (V0CTL)

Virtual Channel 0 Resource Status (V0STS)

Virtual Channel 1 Resource Capability (V1VCRC)

Virtual Channel 1 Resource Control (V1CTL)

Virtual Channel 1 Resource Status (V1STS)

DPC Extended Capability Header (DPCECH)

DPC Capability Register (DPCCAPR)

DPC Control Register (DPCCTLR)

DPC Status Register (DPCSR)

DPC Error Source ID Register (DPCESIDR)

RP PIO Status Register (RPPIOSR)

RP PIO Mask Register (RPPIOMR)

RP PIO Severity Register (RPPIOVR)

RP PIO SysError Register (RPPIOSER)

RP PIO Exception Register (RPPIOER)

RP PIO Header Log DW1 Register (RPPIOHLR_DW1)

RP PIO Header Log DW2 Register (RPPIOHLR_DW2)

RP PIO Header Log DW3 Register (RPPIOHLR_DW3)

RP PIO Header Log DW4 Register (RPPIOHLR_DW4)

Secondary PCI Express Extended Capability Header (SPEECH)

Link Control 3 (LCTL3)

Lane Error Status (LES)

Lane 0 And Lane 1 Equalization Control (L01EC)

Lane 2 And Lane 3 Equalization Control (L23EC)

Lane 4 And Lane 5 Equalization Control (L45EC)

Lane 6 And Lane 7 Equalization Control (L67EC)

Lane 8 And Lane 9 Equalization Control (L89EC)

Lane 10 And Lane 11 Equalization Control (L1011EC)

Lane 12 And Lane 13 Equalization Control (L1213EC)

Lane 14 And Lane 15 Equalization Control (L1415EC)

Data Link Feature Extended Capability Header (DLFECH)

Data Link Feature Capabilities Register (DLFCAP)

Data Link Feature Status Register (DLFSTS)

Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH)

Physical Layer 16.0 GT/s Capability Register (PL16CAP)

Physical Layer 16.0 GT/s Control Register (PL16CTL)

Physical Layer 16.0 GT/s Status Register (PL16S)

Physical Layer 16.0 GT/s Local Data Parity Mismatch Status Register (PL16LDPMS)

Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS)

Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS)

Physical Layer 16.0 GT/s Extra Status Register (PL16ES)

Physical Layer 16.0 GT/s Lane 01 Equalization Control Register (PL16L01EC)

Physical Layer 16.0 GT/s Lane 23 Equalization Control Register (PL16L23EC)

Physical Layer 16.0 GT/s Lane 45 Equalization Control Register (PL16L45EC)

Physical Layer 16.0 GT/s Lane 67 Equalization Control Register (PL16L67EC)

Physical Layer 16.0 GT/s Lane 89 Equalization Control Register (PL16L89EC)

Physical Layer 16.0 GT/s Lane 1011 Equalization Control Register (PL16L1011EC)

Physical Layer 16.0 GT/s Lane 1213 Equalization Control Register (PL16L1213EC)

Physical Layer 16.0 GT/s Lane 1415 Equalization Control Register (PL16L1415EC)

Physical Layer 32.0 GT/s Extended Capability Header (G5ECH)

Physical Layer 32.0 GT/s Capability Register (G5CAP)

Physical Layer 32.0 GT/s Control Register (G5CTL)

Physical Layer 32.0 GT/s Status Register (G5STS)

Receiver Modified TS Data 1 Register (RCVDMODTSDATA1)

Receiver Modified TS Data 2 Register (RCVDMODTSDATA2)

Transmitted Modified TS Data 1 Register (TRNSMODTSDATA1)

Transmitted Modified TS Data 2 Register (TRNSMODTSDATA2)

32.0 GT/s Lane 0123 Equalization Control Register (G5LANEEQCTL_0)

32.0 GT/s Lane 4567 Equalization Control Register (G5LANEEQCTL_4)

32.0 GT/s Lane 891011 Equalization Control Register (G5LANEEQCTL_8)

32.0 GT/s Lane 12131415 Equalization Control Register (G5LANEEQCTL_12)

Alternate Protocol Extended Capability Header (APEC)

Alternate Protocol Capabilities Register (APCAPR)

Alternate Protocol Control Register (APCTRLR)

Alternate Protocol Data 1 Register (APD1R)

Alternate Protocol Data 2 Register (APD2R)

Alternate Protocol Selective Enable Mask Register (APSEMR)

Multicast Extended Capability Header (MCECH)

Multicast Extended Capability Register (MCAPR)

Multicast Control Register (MCCTLR)

Multicast Base Address Register 1 (MCBADRR1)

Multicast Base Address Register 2 (MCBADRR2)

Multicast Receive Register (MCRR)

Multicast Block All Register (MCBAR)

Multicast Block Untranslated Register (MCBUR)

Multicast Overlay BAR 1 (MCOB1)

Multicast Overlay BAR 2 (MCOB2)

VNN Removal Control (VNNREMCTL)

VNN Removal Save And Restore Hardware Contexts 1 (VNNRSNRC1)

Physical Layer 16.0 GT/s Margining Extended Capability Header (PL16MECH)

Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status Byte 0 & 1 (PL16MPCPSB01)

Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status Byte 2 & 3 (PL16MPCPSB23)

Physical Layer 16.0 GT/s Lane0 Margin Control and Status Register (PL16L0MCS)

Physical Layer 16.0 GT/s Lane1 Margin Control and Status Register (PL16L1MCS)

Physical Layer 16.0 GT/s Lane2 Margin Control and Status Register (PL16L2MCS)

Physical Layer 16.0 GT/s Lane3 Margin Control and Status Register (PL16L3MCS)

Physical Layer 16.0 GT/s Lane4 Margin Control and Status Register (PL16L4MCS)

Physical Layer 16.0 GT/s Lane5 Margin Control and Status Register (PL16L5MCS)

Physical Layer 16.0 GT/s Lane6 Margin Control and Status Register (PL16L6MCS)

Physical Layer 16.0 GT/s Lane7 Margin Control and Status Register (PL16L7MCS)

Physical Layer 16.0 GT/s Lane8 Margin Control and Status Register (PL16L8MCS)

Physical Layer 16.0 GT/s Lane9 Margin Control and Status Register (PL16L9MCS)

Physical Layer 16.0 GT/s Lane10 Margin Control and Status Register (PL16L10MCS)

Physical Layer 16.0 GT/s Lane11 Margin Control and Status Register (PL16L11MCS)

Physical Layer 16.0 GT/s Lane12 Margin Control and Status Register (PL16L12MCS)

Physical Layer 16.0 GT/s Lane13 Margin Control and Status Register (PL16L13MCS)

Physical Layer 16.0 GT/s Lane14 Margin Control and Status Register (PL16L14MCS)

Physical Layer 16.0 GT/s Lane15 Margin Control and Status Register (PL16L15MCS)

PMC I/O

Power Management 1 Enables and Status (PM1_EN_STS)

Power Management 1 Control (PM1_CNT)

Power Management 1 Timer (PM1_TMR)

Therm Timer Delay Register (THERM_TIMER_DELAY)

SMI Control and Enable (SMI_EN)

SMI Status Register (SMI_STS)

General Purpose Event Control (GPE_CTRL)

PM2a Control Block (PM2A_CNT_BLK)

Over-Clocking WDT Control (OC_WDT_CTL)

General Purpose Event 0 Status [31:0] (GPE0_STS_31_0)

General Purpose Event 0 Status [63:32] (GPE0_STS_63_32)

General Purpose Event 0 Status [95:64] (GPE0_STS_95_64)

General Purpose Event 0 Status [127:96] (GPE0_STS_127_96)

General Purpose Event 0 Enable [31:0] (GPE0_EN_31_0)

General Purpose Event 0 Enable [63:32] (GPE0_EN_63_32)

General Purpose Event 0 Enable [95:64] (GPE0_EN_95_64)

General Purpose Event 0 Enable [127:96] (GPE0_EN_127_96)

PMC MMIO

PMC MMIO General PM Configuration A (GEN_PMCON_A) General PM Configuration B (GEN_PMCON_B) Configured Revision ID (CRID) Extended Test Mode Register 3 (ETR3) SET STRAP MSG LOCK (SSML) SET STRAP MSG CONTROL (SSMC) SET STRAP MSG DATA (SSMD) Configured Revision ID (CRID_UIP) SLP S0 DEBUG REG0 (SLP_S0_DBG_0) SLP S0 DEBUG REG1 (SLP_S0_DBG_1) SLP S0 DEBUG REG2 (SLP_S0_DBG_2) HSIO Power Management Configuration Reg 1 (MODPHY_PM_CFG1) HSIO Power Management Configuration Reg 2 (MODPHY_PM_CFG2) HSIO Power Management Configuration Reg 3 (MODPHY_PM_CFG3) HSIO Power Management Configuration Reg 4 (MODPHY_PM_CFG4) HSIO Power Management Configuration Reg 5 (MODPHY_PM_CFG5) HSIO Power Management Configuration Reg 6 (MODPHY_PM_CFG6) EXT FET RAMP CFG (EXT_FET_RAMP_CFG) VCCIN AUX CONFIG Register (VCCIN_AUX_CFG) Always Running Timer Value 31:0 (ARTV_31_0) Always Running Timer Value 31:0 (ARTV_63_32) Timed GPIO Control 0 (TGPIOCTL0) Timed GPIO 0 Comparator Value 31:0 (TGPIOCOMPV0_31_0) Timed GPIO Comparator Value 63:32 (TGPIOCOMPV0_63_32) Timed GPIO0 Periodic Interval Value 31_0 (TGPIOPIV0_31_0) Timed GPIO 0 Periodic Interval Value 63_32 (TGPIOPIV0_63_32) Timed GPIO Time Capture Register 31_0 (TGPIOTCV0_31_0) Timed GPIO0 Time Capture Register 63_32 (TGPIOTCV0_63_32) Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV0_31_0) Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV0_63_32) Timed GPIO0 Event Counter Register 31_0 (TGPIOEC0_31_0) Timed GPIO0 Event Counter Register 63_32 (TGPIOEC0_63_32) Timed GPIO Control 1 (TGPIOCTL1) Timed GPIO 1 Comparator Value 31:0 (TGPIOCOMPV1_31_0) Timed GPIO Comparator Value 63:32 (TGPIOCOMPV1_63_32) Timed GPIO1 Periodic Interval Value 31_0 (TGPIOPIV1_31_0) Timed GPIO 1 Periodic Interval Value 63_32 (TGPIOPIV1_63_32) Timed GPIO Time Capture Register 31_0 (TGPIOTCV1_31_0) Timed GPIO Time Capture Register 63_32 (TGPIOTCV1_63_32) Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV1_31_0) Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV1_63_32) Timed GPIO1 Event Counter Register 31_0 (TGPIOEC1_31_0) Timed GPIO Event Counter Register 63_32 (TGPIOEC1_63_32) Min Temperature (MIN_TEMP) Max Temperature (MAX_TEMP) Catastrophic Trip Point Enable (CTEN) EC Thermal Sensor Reporting Enable (ECRPTEN) Throttle Level (TL) Throttle Levels Enable (TLEN) Thermal Sensor Alert High Value (TSAHV) Thermal Sensor Alert Low Value (TSALV) Thermal Alert Trip Status (TAS) Processor Hot Level Control (PHLC) Temperature Sensor Control and Status (TSS0) Wake Alarm Device Timer: AC (WADT_AC) Wake Alarm Device Timer: DC (WADT_DC) Wake Alarm Device Expired Timer: AC (WADT_EXP_AC) Wake Alarm Device Expired Timer: DC (WADT_EXP_DC) Power and Reset Status (PRSTS) Power Management Configuration Reg 1 (PM_CFG) S3 Power Gating Policies (S3_PWRGATE_POL) S4 Power Gating Policies (S4_PWRGATE_POL) S5 Power Gating Policies (S5_PWRGATE_POL) DeepSx Configuration (DSX_CFG) Power Management Configuration Reg 2 (PM_CFG2) Chipset Initialization Register 18E0 (PM_CFG3) Compute Tile Early Power-on Configuration (CPU_EPOC) ACPI Timer Control (ACPI_TMR_CTL) Last TSC Alarm Value[31:0] (TSC_ALARM_LO) Last TSC Alarm Value[63:32] (TSC_ALARM_HI) GPIO Configuration (GPIO_CFG) Host Partition Reset Causes (HPR_CAUSE0) Latency Limit Residency 0 (LAT_LIM_RES_0) Latency Limit Residency 1 (LAT_LIM_RES_1) Latency Limit Residency 2 (LAT_LIM_RES_2) SLP_S0 Residency (SLP_S0_RESIDENCY) Latency Limit Control (LATENCY_LIMIT_CONTROL) Chipset Initialization Register 1B1C (CPPMVRIC) Chipset initialization 1B4C (CPPMVRIC2) CWB MDID Status Register (CWBMDIDSTATUS) ACPI Control (ACTL) S0 Residency (S0_RES) PGD PG_ACK Status Register 0 (PPASR0) PGD PG_ACK Status Register 1 (PPASR1) PGD PFET Enable Ack Status Register 0 (PPFEAR0) PGD PFET Enable Ack Status Register 1 (PPFEAR1) PGD PG_REQ Status Register 0 (PPRSR0) PGD PG_REQ Status Register 1 (PPRSR1) ST_PG_FDIS_PMC - Register 1 (ST_PG_FDIS_PMC_1) ST_PG_FDIS_PMC - Register 2 (ST_PG_FDIS_PMC_2) LPM CSOFF_MPFPW5_0_PLL BLK CNTR (LPM_CSOFF_MPFPW5_0_PLL_BLK_CNTR) LPM CSOFF_MPFPW4_0_PLL BLK CNTR (LPM_CSOFF_MPFPW4_0_PLL_BLK_CNTR) LPM CSOFF_G5FPW_1_PLL BLK CNTR (LPM_CSOFF_G5FPW_1_PLL_BLK_CNTR) LPM MISC_VNN_SOC BLK CNTR (LPM_MISC_VNN_SOC_BLK_CNTR) LPM AGTPGATED_SPE_PGD0 BLK CNTR (LPM_AGTPGATED_SPE_PGD0_BLK_CNTR) LPM AGTPGATED_SPD_PGD0 BLK CNTR (LPM_AGTPGATED_SPD_PGD0_BLK_CNTR) LPM AGTPGATED_GBETSN_PGD0 BLK CNTR (LPM_AGTPGATED_GBETSN_PGD0_BLK_CNTR) LPM AGTPGATED_GBETSN1_PGD0 BLK CNTR (LPM_AGTPGATED_GBETSN1_PGD0_BLK_CNTR) LPM AGTPGATED_SPF_PGD0 BLK CNTR (LPM_AGTPGATED_SPF_PGD0_BLK_CNTR) LPM CSOFF_G5FPW_0_PLL BLK CNTR (LPM_CSOFF_G5FPW_0_PLL_BLK_CNTR)

General PM Configuration A (GEN_PMCON_A)

General PM Configuration B (GEN_PMCON_B)

Configured Revision ID (CRID)

Extended Test Mode Register 3 (ETR3)

SET STRAP MSG LOCK (SSML)

SET STRAP MSG CONTROL (SSMC)

SET STRAP MSG DATA (SSMD)

Configured Revision ID (CRID_UIP)

SLP S0 DEBUG REG0 (SLP_S0_DBG_0)

SLP S0 DEBUG REG1 (SLP_S0_DBG_1)

SLP S0 DEBUG REG2 (SLP_S0_DBG_2)

HSIO Power Management Configuration Reg 1 (MODPHY_PM_CFG1)

HSIO Power Management Configuration Reg 2 (MODPHY_PM_CFG2)

HSIO Power Management Configuration Reg 3 (MODPHY_PM_CFG3)

HSIO Power Management Configuration Reg 4 (MODPHY_PM_CFG4)

HSIO Power Management Configuration Reg 5 (MODPHY_PM_CFG5)

HSIO Power Management Configuration Reg 6 (MODPHY_PM_CFG6)

EXT FET RAMP CFG (EXT_FET_RAMP_CFG)

VCCIN AUX CONFIG Register (VCCIN_AUX_CFG)

Always Running Timer Value 31:0 (ARTV_31_0)

Always Running Timer Value 31:0 (ARTV_63_32)

Timed GPIO Control 0 (TGPIOCTL0)

Timed GPIO 0 Comparator Value 31:0 (TGPIOCOMPV0_31_0)

Timed GPIO Comparator Value 63:32 (TGPIOCOMPV0_63_32)

Timed GPIO0 Periodic Interval Value 31_0 (TGPIOPIV0_31_0)

Timed GPIO 0 Periodic Interval Value 63_32 (TGPIOPIV0_63_32)

Timed GPIO Time Capture Register 31_0 (TGPIOTCV0_31_0)

Timed GPIO0 Time Capture Register 63_32 (TGPIOTCV0_63_32)

Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV0_31_0)

Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV0_63_32)

Timed GPIO0 Event Counter Register 31_0 (TGPIOEC0_31_0)

Timed GPIO0 Event Counter Register 63_32 (TGPIOEC0_63_32)

Timed GPIO Control 1 (TGPIOCTL1)

Timed GPIO 1 Comparator Value 31:0 (TGPIOCOMPV1_31_0)

Timed GPIO Comparator Value 63:32 (TGPIOCOMPV1_63_32)

Timed GPIO1 Periodic Interval Value 31_0 (TGPIOPIV1_31_0)

Timed GPIO 1 Periodic Interval Value 63_32 (TGPIOPIV1_63_32)

Timed GPIO Time Capture Register 31_0 (TGPIOTCV1_31_0)

Timed GPIO Time Capture Register 63_32 (TGPIOTCV1_63_32)

Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV1_31_0)

Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV1_63_32)

Timed GPIO1 Event Counter Register 31_0 (TGPIOEC1_31_0)

Timed GPIO Event Counter Register 63_32 (TGPIOEC1_63_32)

Min Temperature (MIN_TEMP)

Max Temperature (MAX_TEMP)

Catastrophic Trip Point Enable (CTEN)

EC Thermal Sensor Reporting Enable (ECRPTEN)

Throttle Level (TL)

Throttle Levels Enable (TLEN)

Thermal Sensor Alert High Value (TSAHV)

Thermal Sensor Alert Low Value (TSALV)

Thermal Alert Trip Status (TAS)

Processor Hot Level Control (PHLC)

Temperature Sensor Control and Status (TSS0)

Wake Alarm Device Timer: AC (WADT_AC)

Wake Alarm Device Timer: DC (WADT_DC)

Wake Alarm Device Expired Timer: AC (WADT_EXP_AC)

Wake Alarm Device Expired Timer: DC (WADT_EXP_DC)

Power and Reset Status (PRSTS)

Power Management Configuration Reg 1 (PM_CFG)

S3 Power Gating Policies (S3_PWRGATE_POL)

S4 Power Gating Policies (S4_PWRGATE_POL)

S5 Power Gating Policies (S5_PWRGATE_POL)

DeepSx Configuration (DSX_CFG)

Power Management Configuration Reg 2 (PM_CFG2)

Chipset Initialization Register 18E0 (PM_CFG3)

Compute Tile Early Power-on Configuration (CPU_EPOC)

ACPI Timer Control (ACPI_TMR_CTL)

Last TSC Alarm Value[31:0] (TSC_ALARM_LO)

Last TSC Alarm Value[63:32] (TSC_ALARM_HI)

GPIO Configuration (GPIO_CFG)

Host Partition Reset Causes (HPR_CAUSE0)

Latency Limit Residency 0 (LAT_LIM_RES_0)

Latency Limit Residency 1 (LAT_LIM_RES_1)

Latency Limit Residency 2 (LAT_LIM_RES_2)

SLP_S0 Residency (SLP_S0_RESIDENCY)

Latency Limit Control (LATENCY_LIMIT_CONTROL)

Chipset Initialization Register 1B1C (CPPMVRIC)

Chipset initialization 1B4C (CPPMVRIC2)

CWB MDID Status Register (CWBMDIDSTATUS)

ACPI Control (ACTL)

S0 Residency (S0_RES)

PGD PG_ACK Status Register 0 (PPASR0)

PGD PG_ACK Status Register 1 (PPASR1)

PGD PFET Enable Ack Status Register 0 (PPFEAR0)

PGD PFET Enable Ack Status Register 1 (PPFEAR1)

PGD PG_REQ Status Register 0 (PPRSR0)

PGD PG_REQ Status Register 1 (PPRSR1)

ST_PG_FDIS_PMC - Register 1 (ST_PG_FDIS_PMC_1)

ST_PG_FDIS_PMC - Register 2 (ST_PG_FDIS_PMC_2)

LPM CSOFF_MPFPW5_0_PLL BLK CNTR (LPM_CSOFF_MPFPW5_0_PLL_BLK_CNTR)

LPM CSOFF_MPFPW4_0_PLL BLK CNTR (LPM_CSOFF_MPFPW4_0_PLL_BLK_CNTR)

LPM CSOFF_G5FPW_1_PLL BLK CNTR (LPM_CSOFF_G5FPW_1_PLL_BLK_CNTR)

LPM MISC_VNN_SOC BLK CNTR (LPM_MISC_VNN_SOC_BLK_CNTR)

LPM AGTPGATED_SPE_PGD0 BLK CNTR (LPM_AGTPGATED_SPE_PGD0_BLK_CNTR)

LPM AGTPGATED_SPD_PGD0 BLK CNTR (LPM_AGTPGATED_SPD_PGD0_BLK_CNTR)

LPM AGTPGATED_GBETSN_PGD0 BLK CNTR (LPM_AGTPGATED_GBETSN_PGD0_BLK_CNTR)

LPM AGTPGATED_GBETSN1_PGD0 BLK CNTR (LPM_AGTPGATED_GBETSN1_PGD0_BLK_CNTR)

LPM AGTPGATED_SPF_PGD0 BLK CNTR (LPM_AGTPGATED_SPF_PGD0_BLK_CNTR)

LPM CSOFF_G5FPW_0_PLL BLK CNTR (LPM_CSOFF_G5FPW_0_PLL_BLK_CNTR)

PMC PCI Configuration

PMC PCI Configuration Device Vendor ID (DEVVENDID) STATUSCOMMAND Status and Command (STATUSCOMMAND) Revision Class Codes (REVCLASSCODE) CLLATHEADERBIST Cache Line Latency Header And BIST (CLLATHEADERBIST) 32-bit Base Address Register (BAR) BAR HIGH (BAR_HIGH) 32-bit Base Address Register1 (BAR1) BAR1 HIGH (BAR1_HIGH) Bar 2 (BAR2) Subsystem Identifiers (SUBSYSTEMID) EXPANSION ROM BASEADDR (EXPANSION_ROM_BASEADDR) CAPABILITY PTR (CAPABILITYPTR) INTERRUPT REG Interrupt Register (INTERRUPTREG) POWER CAP ID PowerManagement Capability ID (POWERCAPID) PME CTRL STATUS (PMECTRLSTATUS) PCIDEVIDLE CAP RECORD (PCIDEVIDLE_CAP_RECORD) DEVID VEND SPECIFIC REG (DEVID_VEND_SPECIFIC_REG) D0I3 CONTROL SW LTR MMIO REG (D0I3_CONTROL_SW_LTR_MMIO_REG) DEVICE IDLE POINTER REG (DEVICE_IDLE_POINTER_REG) D0I3 MAX POW LAT PG CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG) GEN REG RW1 (GEN_REGRW1) GEN REG RW2 (GEN_REGRW2) GEN REG RW3 (GEN_REGRW3) GEN REG RW4 (GEN_REGRW4) GEN INPUT REG (GEN_INPUT_REG)

Device Vendor ID (DEVVENDID)

STATUSCOMMAND Status and Command (STATUSCOMMAND)

Revision Class Codes (REVCLASSCODE)

CLLATHEADERBIST Cache Line Latency Header And BIST (CLLATHEADERBIST)

32-bit Base Address Register (BAR)

BAR HIGH (BAR_HIGH)

32-bit Base Address Register1 (BAR1)

BAR1 HIGH (BAR1_HIGH)

Bar 2 (BAR2)

Subsystem Identifiers (SUBSYSTEMID)

EXPANSION ROM BASEADDR (EXPANSION_ROM_BASEADDR)

CAPABILITY PTR (CAPABILITYPTR)

INTERRUPT REG Interrupt Register (INTERRUPTREG)

POWER CAP ID PowerManagement Capability ID (POWERCAPID)

PME CTRL STATUS (PMECTRLSTATUS)

PCIDEVIDLE CAP RECORD (PCIDEVIDLE_CAP_RECORD)

DEVID VEND SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)

D0I3 CONTROL SW LTR MMIO REG (D0I3_CONTROL_SW_LTR_MMIO_REG)

DEVICE IDLE POINTER REG (DEVICE_IDLE_POINTER_REG)

D0I3 MAX POW LAT PG CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG)

GEN REG RW1 (GEN_REGRW1)

GEN REG RW2 (GEN_REGRW2)

GEN REG RW3 (GEN_REGRW3)

GEN REG RW4 (GEN_REGRW4)

GEN INPUT REG (GEN_INPUT_REG)

SSRAM PCI Configuration

SSRAM PCI Configuration Device Vendor ID (DEVVENDID) STATUSCOMMAND Status and Command (STATUSCOMMAND) Revision Class Codes (REVCLASSCODE) CLLATHEADERBIST Cache Line Latency Header And BIST (CLLATHEADERBIST) 32-bit Base Address Register (BAR) BAR HIGH (BAR_HIGH) 32-bit Base Address Register1 (BAR1) BAR1 HIGH (BAR1_HIGH) Subsystem Identifiers (SUBSYSTEMID) EXPANSION ROM BASEADDR (EXPANSION_ROM_BASEADDR) CAPABILITY PTR (CAPABILITYPTR) INTERRUPT REG Interrupt Register (INTERRUPTREG) POWER CAP ID PowerManagement Capability ID (POWERCAPID) PME CTRL STATUS (PMECTRLSTATUS) PCIDEVIDLE CAP RECORD (PCIDEVIDLE_CAP_RECORD) DEVID VEND SPECIFIC REG (DEVID_VEND_SPECIFIC_REG) D0I3 CONTROL SW LTR MMIO REG (D0I3_CONTROL_SW_LTR_MMIO_REG) DEVICE IDLE POINTER REG (DEVICE_IDLE_POINTER_REG) D0I3 MAX POW LAT PG CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG) GEN REG RW1 (GEN_REGRW1) GEN REG RW2 (GEN_REGRW2) GEN REG RW3 (GEN_REGRW3) GEN REG RW4 (GEN_REGRW4) GEN INPUT REG (GEN_INPUT_REG)

Device Vendor ID (DEVVENDID)

STATUSCOMMAND Status and Command (STATUSCOMMAND)

Revision Class Codes (REVCLASSCODE)

CLLATHEADERBIST Cache Line Latency Header And BIST (CLLATHEADERBIST)

32-bit Base Address Register (BAR)

BAR HIGH (BAR_HIGH)

32-bit Base Address Register1 (BAR1)

BAR1 HIGH (BAR1_HIGH)

Subsystem Identifiers (SUBSYSTEMID)

EXPANSION ROM BASEADDR (EXPANSION_ROM_BASEADDR)

CAPABILITY PTR (CAPABILITYPTR)

INTERRUPT REG Interrupt Register (INTERRUPTREG)

POWER CAP ID PowerManagement Capability ID (POWERCAPID)

PME CTRL STATUS (PMECTRLSTATUS)

PCIDEVIDLE CAP RECORD (PCIDEVIDLE_CAP_RECORD)

DEVID VEND SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)

D0I3 CONTROL SW LTR MMIO REG (D0I3_CONTROL_SW_LTR_MMIO_REG)

DEVICE IDLE POINTER REG (DEVICE_IDLE_POINTER_REG)

D0I3 MAX POW LAT PG CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG)

GEN REG RW1 (GEN_REGRW1)

GEN REG RW2 (GEN_REGRW2)

GEN REG RW3 (GEN_REGRW3)

GEN REG RW4 (GEN_REGRW4)

GEN INPUT REG (GEN_INPUT_REG)

USB xHCI MMIO

Capability Registers Length (CAPLENGTH)

Host Controller Interface Version Number (HCIVERSION)

Structural Parameters 1 (HCSPARAMS1)

Structural Parameters 2 (HCSPARAMS2)

Structural Parameters 3 (HCSPARAMS3)

Capability Parameters (HCCPARAMS)

Doorbell Offset (DBOFF)

Runtime Register Space Offset (RTSOFF)

USB Command (USBCMD)

USB Status (USBSTS)

Page Size (PAGESIZE)

Device Notification Control (DNCTRL)

Command Ring Low (CRCR_LO)

Command Ring High (CRCR_HI)

Device Context Base Address Array Pointer Low (DCBAAP_LO)

Device Context Base Address Array Pointer High (DCBAAP_HI)

Configure Reg (CONFIG)

Port Status AndControl USB2 (PORTSC1)

Port Power Management Status Aand Control USB2 (PORTPMSC1)

Port X Hardware LPM Control Register (PORTHLPMC1)

Port Status And Control USB3 (PORTSC2)

Port Power Management Status And Control USB3 (PORTPMSC2)

USB3 Port Link Info (PORTLI2)

Port Status And Control USB3 (PORTSC3)

Port Power Management Status And Control USB3 (PORTPMSC3)

USB3 Port Link Info (PORTLI3)

Port Status And Control USB3 (PORTSC4)

Port Power Management Status And Control USB3 (PORTPMSC4)

USB3 Port Link Info (PORTLI4)

Port Status And Control USB3 (PORTSC5)

Port Power Management Status And Control USB3 (PORTPMSC5)

USB3 Port Link Info (PORTLI5)

Microframe Index (RTMFINDEX)

Interrupter Management (IMAN0)

Interrupter Moderation (IMOD0)

Event Ring Segment Table Size (ERSTSZ0)

Event Ring Segment Table Base Address Low (ERSTBA_LO0)

Event Ring Segment Table Base Address High (ERSTBA_HI0)

Event Ring Dequeue Pointer Low (ERDP_LO0)

Event Ring Dequeue Pointer High (ERDP_HI0)

Interrupter Management (IMAN1)

Interrupter Moderation (IMOD1)

Event Ring Segment Table Size (ERSTSZ1)

Event Ring Segment Table Base Address Low (ERSTBA_LO1)

Event Ring Segment Table Base Address High (ERSTBA_HI1)

Event Ring Dequeue Pointer Low (ERDP_LO1)

Event Ring Dequeue Pointer High (ERDP_HI1)

Interrupter Management (IMAN2)

Interrupter Moderation (IMOD2)

Event Ring Segment Table Size (ERSTSZ2)

Event Ring Segment Table Base Address Low (ERSTBA_LO2)

Event Ring Segment Table Base Address High (ERSTBA_HI2)

Event Ring Dequeue Pointer Low (ERDP_LO2)

Event Ring Dequeue Pointer High (ERDP_HI2)

Interrupter Management (IMAN3)

Interrupter Moderation (IMOD3)

Event Ring Segment Table Size (ERSTSZ3)

Event Ring Segment Table Base Address Low (ERSTBA_LO3)

Event Ring Segment Table Base Address High (ERSTBA_HI3)

Event Ring Dequeue Pointer Low (ERDP_LO3)

Event Ring Dequeue Pointer High (ERDP_HI3)

Interrupter Management (IMAN4)

Interrupter Moderation (IMOD4)

Event Ring Segment Table Size (ERSTSZ4)

Event Ring Segment Table Base Address Low (ERSTBA_LO4)

Event Ring Segment Table Base Address High (ERSTBA_HI4)

Event Ring Dequeue Pointer Low (ERDP_LO4)

Event Ring Dequeue Pointer High (ERDP_HI4)

Interrupter Management (IMAN5)

Interrupter Moderation (IMOD5)

Event Ring Segment Table Size (ERSTSZ5)

Event Ring Segment Table Base Address Low (ERSTBA_LO5)

Event Ring Segment Table Base Address High (ERSTBA_HI5)

Event Ring Dequeue Pointer Low (ERDP_LO5)

Event Ring Dequeue Pointer High (ERDP_HI5)

Interrupter Management (IMAN6)

Interrupter Moderation (IMOD6)

Event Ring Segment Table Size (ERSTSZ6)

Event Ring Segment Table Base Address Low (ERSTBA_LO6)

Event Ring Segment Table Base Address High (ERSTBA_HI6)

Event Ring Dequeue Pointer Low (ERDP_LO6)

Event Ring Dequeue Pointer High (ERDP_HI6)

Interrupter Management (IMAN7)

Interrupter Moderation (IMOD7)

Event Ring Segment Table Size (ERSTSZ7)

Event Ring Segment Table Base Address Low (ERSTBA_LO7)

Event Ring Segment Table Base Address High (ERSTBA_HI7)

Event Ring Dequeue Pointer Low (ERDP_LO7)

Event Ring Dequeue Pointer High (ERDP_HI7)

XECP SUPP USB2_0 (XECP_SUPP_USB2_0)

XECP SUPP USB2_1 (XECP_SUPP_USB2_1)

XECP SUPP USB2_2 (XECP_SUPP_USB2_2)

XECP SUPP USB3_3 (XECP_SUPP_USB2_3)

XECP SUPP USB2_4 Full Speed (XECP_SUPP_USB2_4)

XECP_SUPP USB2_5 Low Speed (XECP_SUPP_USB2_5)

XECP SUPP USB2_6 High Speed (XECP_SUPP_USB2_6)

XECP SUPP USB3_0 (XECP_SUPP_USB3_0)

XECP SUPP USB3_1 (XECP_SUPP_USB3_1)

XECP SUPP USB3_2 (XECP_SUPP_USB3_2)

XECP SUPP USB3_3 (XECP_SUPP_USB3_3)

XECP SUPP USB3_4 (XECP_SUPP_USB3_4)

XECP SUPP USB3_5 (XECP_SUPP_USB3_5)

XECP SUPP USB3_6 (XECP_SUPP_USB3_6)

XECP SUPP USB3_7 (XECP_SUPP_USB3_7)

Host Control Scheduler (HOST_CTRL_SCH_REG)

Power Management Control (PMCTRL_REG)

Host Controller Misc Reg (HOST_CTRL_MISC_REG)

Host Controller Misc Reg2 (HOST_CTRL_MISC_REG2)

Super Speed Port Enable (SSPE_REG)

AUX Power Management Control (AUX_CTRL_REG1)

SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG)

USB2 Port Link Control 1 (USB2_LINK_MGR_CTRL_REG1)

USB2 Port Link Control 2 (USB2_LINK_MGR_CTRL_REG2)

USB2 Port Link Control 3 (USB2_LINK_MGR_CTRL_REG3)

USB2 Port Link Control 4 (USB2_LINK_MGR_CTRL_REG4)

Power Scheduler Control-0 (PWR_SCHED_CTRL0)

Power Scheduler Control-1 (PWR_SCHED_CTRL2)

AUX Power Management Control (AUX_CTRL_REG2)

USB2 PHY Power Management Control (USB2_PHY_PMC)

XHCI Aux Clock Control Register (XHCI_AUX_CCR)

XHC Latency Tolerance Parameters LTV Control (XLTP_LTV1)

XHC Latency Tolerance Parameters LTV Control 2 (XLTP_LTV2)

XHC Latency Tolerance Parameters High Idle Time Control (XLTP_HITC)

XHC Latency Tolerance Parameters Medium Idle Time Control (XLTP_MITC)

XHC Latency Tolerance Parameters Low Idle Time Control (XLTP_LITC)

LFPS On Count (LFPSONCOUNT_REG)

USB2 Power Management Control (USB2PMCTRL_REG)

USB Legacy Support Capability (USBLEGSUP)

USB Legacy Support Control Status (USBLEGCTLSTS)

Port Disable Override Capability Register (PDO_CAPABILITY)

Command Reg (CMD_MMIO)

Device Status (STS_MMIO)

Revision ID (RID_MMIO)

Programming Interface (PI_MMIO)

Sub Class Code (SCC_MMIO)

Base Class Code (BCC_MMIO)

Cache Line Size (CLS_MMIO)

Master Latency Timer (MLT_MMIO)

Header Type (HT_MMIO)

Memory Base Address (MBAR_MMIO)

USB Subsystem Vendor ID (SSVID_MMIO)

USB Subsystem ID (SSID_MMIO)

Capabilities Pointer (CAP_PTR_MMIO)

Interrupt Line (ILINE_MMIO)

Interrupt Pin (IPIN_MMIO)

Serial Bus Release Number (SBRN_MMIO)

Frame Length Adjustment (FLADJ_MMIO)

Best Effort Service Latency (BESL_MMIO)

PCI Power Management Capability ID (PM_CID_MMIO)

Next Item Pointer 1 (PM_NEXT_MMIO)

Power Management Capabilities (PM_CAP_MMIO)

Power Management Control/Status (PM_CS_MMIO)

Message Signaled Interrupt CID (MSI_CID_MMIO)

Next Item Pointer (MSI_NEXT_MMIO)

Message Signaled Interrupt Message Control (MSI_MCTL_MMIO)

Message Signaled Interrupt Message Address (MSI_MAD_MMIO)

Message Signaled Interrupt Upper Address (MSI_MUAD_MMIO)

Message Signaled Interrupt Message Data (MSI_MD_MMIO)

High Speed Configuration 2 (HSCFG2_MMIO)

Debug Capability ID Register (DCID)

Debug Capability Doorbell Register (DCDB)

Debug Capability Event Ring Segment Table Size Register (DCERSTSZ)

Debug Capability Event Ring Segment Table Base Address Register (DCERSTBA)

Debug Capability Event Ring Dequeue Pointer Register (DCERDP)

Debug Capability Control Register (DCCTRL)

Debug Capability Status Register (DCST)

Debug Capability Port Status And Control Register (DCPORTSC)

Debug Capability Context Pointer Register (DCCP)

Fuse and Strap Mirror Capability Register (FUSE_AND_STRAP_MIRROR_CAP_REG)

GLOBAL TIME SYNC CAP REG (GLOBAL_TIME_SYNC_CAP_REG)

GLOBAL TIME SYNC CTRL REG (GLOBAL_TIME_SYNC_CTRL_REG)

MICROFRAME TIME REG (MICROFRAME_TIME_REG)

Global Time Value (Low Register) (GLOBAL_TIME_LOW_REG)

GLOBAL TIME HI REG (GLOBAL_TIME_HI_REG)

Dublin HOST_CTRL_USB3_LOCAL_LPBK_RPTR (HOST_CTRL_USB3_LOCAL_LPBK_RPTR)

Host Ctrl Usb3 Master Loopback Register (HOST_CTRL_USB3_MSTR_LPBK)

Host Ctrl Usb3 Blr Comp Register (HOST_CTRL_USB3_BLR_COMP)

Host Ctrl Ssp Dis Register (HOST_CTRL_SSP_DIS)

XHCI USB2 Overcurrent Pin Mapping (U2OCM1)

XHCI USB2 Overcurrent Pin Mapping (U2OCM2)

XHCI USB2 Overcurrent Pin Mapping (U2OCM3)

XHCI USB2 Overcurrent Pin Mapping (U2OCM4)

XHCI USB3 Overcurrent Pin Mapping (U3OCM1)

XHCI USB3 Overcurrent Pin Mapping (U3OCM2)

SAI Policy Capability Register (SAI_POLICY_CAP_REG)

USB xHCI PCI Configuration

USB xHCI PCI Configuration Vendor ID (VID) Device ID (DID) Command Reg (CMD) Device Status (STS) Revision ID (RID) Programming Interface (PI) Sub Class Code (SCC) Base Class Code (BCC) Cache Line Size (CLS) Master Latency Timer (MLT) Header Type (HT) Memory Base Address (MBAR) USB Subsystem Vendor ID (SSVID) USB Subsystem ID (SSID) Capabilities Pointer (CAP_PTR) Interrupt Line (ILINE) Interrupt Pin (IPIN) XHC System Bus Configuration 1 (XHCC1) XHC System Bus Configuration 2 (XHCC2) Clock Gating (XHCLKGTEN) Audio Time Synchronization (AUDSYNC) Serial Bus Release Number (SBRN) Frame Length Adjustment (FLADJ) Best Effort Service Latency (BESL) PCI Power Management Capability ID (PM_CID) Next Item Pointer 1 (PM_NEXT) Power Management Capabilities (PM_CAP) Power Management Control/Status (PM_CS) Message Signaled Interrupt CID (MSI_CID) Next Item Pointer (MSI_NEXT) Message Signaled Interrupt Message Control (MSI_MCTL) Message Signaled Interrupt Message Address (MSI_MAD) Message Signaled Interrupt Upper Address (MSI_MUAD) Message Signaled Interrupt Message Data (MSI_MD)

Programming Interface (PI)

Sub Class Code (SCC)

Base Class Code (BCC)

Cache Line Size (CLS)

Master Latency Timer (MLT)

Header Type (HT)

Memory Base Address (MBAR)

USB Subsystem Vendor ID (SSVID)

USB Subsystem ID (SSID)

Capabilities Pointer (CAP_PTR)

Interrupt Line (ILINE)

Interrupt Pin (IPIN)

XHC System Bus Configuration 1 (XHCC1)

XHC System Bus Configuration 2 (XHCC2)

Clock Gating (XHCLKGTEN)

Audio Time Synchronization (AUDSYNC)

Serial Bus Release Number (SBRN)

Frame Length Adjustment (FLADJ)

Best Effort Service Latency (BESL)

PCI Power Management Capability ID (PM_CID)

Next Item Pointer 1 (PM_NEXT)

Power Management Capabilities (PM_CAP)

Power Management Control/Status (PM_CS)

Message Signaled Interrupt CID (MSI_CID)

Next Item Pointer (MSI_NEXT)

Message Signaled Interrupt Message Control (MSI_MCTL)

Message Signaled Interrupt Message Address (MSI_MAD)

Message Signaled Interrupt Upper Address (MSI_MUAD)

Message Signaled Interrupt Message Data (MSI_MD)

Introduction
P2SB PCI Configuration
PCI Express* (PCIe*) Configuration (D1:F0)
PCI Express* (PCIe*) Configuration (D6:F1)
PCI Express* (PCIe*) Configuration (D6:F2)
PMC I/O
PMC MMIO
PMC PCI Configuration
SSRAM PCI Configuration
USB xHCI MMIO
USB xHCI PCI Configuration

Last TSC Alarm Value[63:32] (TSC_ALARM_HI) – Offset 1914

This register is reset by RSMRST#.

Bit Range	Default	Access	Field Name and Description
31:0	0h	RO/V	Last TSC Alarm Value [63:32] (TSC_ALARM_VAL_HI) This field contains bits 63:32 of the last TSC alarm value received from the CPU.

Bit Range

Default

Access

Field Name and Description

31:0

RO/V

Last TSC Alarm Value [63:32] (TSC_ALARM_VAL_HI)

This field contains bits 63:32 of the last TSC alarm value received from the CPU.

GPIO Configuration (GPIO_CFG)

Last TSC Alarm Value[31:0] (TSC_ALARM_LO) GPIO Configuration (GPIO_CFG)