31

0h

RW

SATA Interface Disable Indication (SATA_​DIS_​IND)

When set to 1, this bit indicates that the SATA interface is completely disabled. Therefore, the HSIO lanes normally assigned to SATA will operate through the PCIe controller (or not be used at all).

When cleared, it indicates that at least some of the SATA interface lanes may be used actively by the SATA controller, so none of the lanes assigned to SATA interface can operate through the PCIe controller.

30

0h

RW

Timing t591 (TIMING_​T591)

This field configures t591 timing involved in the over-clocking flow (Wait times between writes from PMC to ICC registers when executing BCLK slow ramp flow)

Note: Encodings are all min timings.

29

0h

RW

Allow 24MHz Crystal Oscillator Shutdown (ALLOW_​24_​OSC_​SD)

When this bit is '0', the 24MHz crystal oscillator will always be running while in S0.

When this bit is '1', the 24MHz crystal oscillator may be shut down in S0 (Cx only) if all other conditions allow.

28

0h

RW

Time Sync Maximum Attempts (TS_​MAXTRY)

The value of this bit determines how many times the PMC will retry time synchronization before stopping and reporting failure to the initiator.



Encoding:

0 Maximum of 5 attempts

1 Maximum of 10 attempts

27

0h

RO

Reserved

26

0h

RW

Boot Media RTD3 Power Management Enable (BMRTD3PME)

0: RTD3 is not enabled. Drive '1' to BOOTMPC pin

1: RTD3 is enabled. Drive the value of BMRTD3PP to BOOTMPC pin

25

0h

RW

Allow USB2 PHY Core Power Gating (ALLOW_​USB2_​CORE_​PG)

When this bit is '0' (default), USB2 PHY power gating is disabled.

When this bit is '1', USB2 PHY power gating can occur if all other required conditions are met.

24

0h

RW/L

Energy Reporting Lock (ER_​LOCK)

When this bit is written to 1, it will remain 1 until the next RSMRST# assertion.
While this bit is 1, GEN_​PMCON_​A.ER_​EN value cannot be changed. BIOS should write 1b1 to this bit only AFTER writing to GEN_​PMCON_​A.ER_​EN.

23:22

0h

RO

Reserved

21

0h

RW

RTC Wake from DeepSx Disable (RTC_​DSX_​WAKE_​DIS)

When set, this bit disables RTC wakes from waking the system from DeepSx.

20

0h

RW

Boot Media RTD3 Reset Management Enable (BMRTD3RME)

0: Boot Media device not in D3. Drive '1' to reset pin

1: Boot Media device in D3. Drive the value of BMRTD3RP to reset pin

19:18

0h

RW/L

SLP_​SUS# Minimum Assertion Width (SLP_​SUS_​MIN_​ASST_​WDTH)

This 2-bit value indicates the minimum assertion width of the SLP_​SUS# signal to guarantee that the SUS well power supplies have been fully power-cycled. This value may be modified per platform depending on power supply capacitance, board capacitance, power failure detection circuits, etc.

Settings are:

00 = 0 ms (i.e. stretching disabled - default)

01 = 500ms

10 = 1s

11 = 4s

This field is not writable when the SLP_​Sx# Stretching Policy Lock- Down bit is set.

This field is ignored when exiting a G3 state if the Disable SLP_​X Stretching After SUS Power Failure bit is set. Note that unlike with all other SLP_​* pin stretching, this disable bit only impacts SLP_​SUS# stretching during G3 exit rather than both G3 and DeepSx exit. SLP_​SUS# stretching always applies to DeepSx regardless of the disable bit.

Programming Note: For platforms that enable DeepSx, BIOS must program SLP_​SUS# stretching to be greater than or equal to the largest stretching value on any other SLP_​* pin (SLP_​S3#, SLP_​S4#, SLP_​LAN#, or SLP_​A#).

This bit is cleared by RTCRST#.

17:16

0h

RW/L

SLP_​A# Minimum Assertion Width (SLP_​A_​MIN_​ASST_​WDTH)

This 2-bit value indicates the minimum assertion width of the SLP_​A# signal to guarantee that the ASW power supplies have been fully power-cycled. This value may be modified per platform depending on power supply capacitance, board capacitance, power failure detection circuits, etc.

Settings are:

00 = 0 ms (i.e. stretching disabled - default)

01 = 4 s

10 = 98 ms

11 = 2 s

This field is not writable when the SLP_​Sx# Stretching Policy Lock- Down bit is set.

This field is ignored when exiting a G3 or DeepSx state if the Disable SLP_​X Stretching After SUS Power Failure bit is set.

This bit is cleared by RTCRST#.

15:14

0h

RW/L

SLP_​LAN# Minimum Assertion Width (SLP_​LAN_​MIN_​ASST_​WDTH)

This 2-bit value indicates the minimum assertion width of the SLP_​LAN# signal to guarantee that the power to the PHY has been fully power-cycled. This value may be modified per platform depending on power supply, capacitance, board capacitance, power failure detection circuits, etc.

This field is not writable when the SLP_​Sx# Stretching Policy Lock Down bit is set to 1.
Encoding:
00 : 0ms, 01: 1ms, 10: 50ms, 11: 2s

13

0h

RW

After G3 Last State Enable (AG3_​LS_​EN)

When PM_​CFG.AG3E is '0', AG3_​LS_​EN determines whether the processor will consider the platform's previous state when determining whether to power-up after G3.



Encodings:

0 (default): The processor power-up policies after G3 do not depend on the platform's state when the G3 occurred.

1: The processor power-up policies after G3 depend on the platform's state when the G3 occurred.

- If the power failure occurred while the platform was in S0 or while in the process of going to S0, the platform will power-up to S0 upon exiting G3.

- If the power failure occurred while the platform was in Sx or while in the process of going to Sx, the platform will stay in S4/S5 upon exiting G3.



Note: This bit applies only when GEN_​PMCON_​3.AG3E is '0'. If AG3E is '1', the platform will always stay in S4/S5 after G3 regardless of the value of AG3_​LS_​EN.

12

0h

RW

After Type 8 Global Reset Last State Enable (A8GR_​LS_​EN)

AGR_​LS_​EN determines whether the processor will consider the platform's previous state when determining whether to power-up after non-thermal and non-explicitly requested type 8 global resets.



Encodings:

0 (default): The processor power-up policies after a global reset do not depend on the platform's state when the reset occurred.

1: The processor power-up policies after a global reset depend on the platform's state when the reset occurred.

If the global reset occurred while the platform was in S0 or while in the process of going to S0, the platform will power-up to S0 after the reset.

If the global reset occurred while the platform was in Sx or while in the process of going to Sx, the platform will stay in S5 upon exiting G3.

11

0h

RW

Global Reset Three Strike Counter Enable (GR_​TSC_​EN)

When set, GR_​TSC_​EN will cause the PMC to keep the platform in S5 after the third consecutive type 7 global reset occurs during the boot flow. The three strike counter is reset in the following situations:

- The system reaches S0

- A type 8 global reset occurs, including after the three strike counter causes the system to stay in S5.

- RSMRST# asserts (due to DeepSx entry or a G3 event occurring)

10

0h

RW

Power Button Debounce Mode (PB_​DB_​MODE)

This bit controls when interrupts (SMI#, SCI) are generated in response to assertion of the PWRBTN# pin. This bit's values cause the following behavior:

- '0': The 16ms debounce period applies to all usages of the PWRBTN# pin (legacy behavior).

- '1': When a falling edge occurs on the PWRBTN# pin, an interrupt is generated and the 16ms debounce timer starts. Subsequent interrupts are masked while the debounce timer is running.

Note: Power button override logic always samples the post-debounce version of the pin.

9:8

0h

RW/L

Reset Power Cycle Duration (PWR_​CYC_​DUR)

The value in this register determines the minimum time a platform will stay in reset (SLP_​S3#, SLP_​S4#, SLP_​S5# asserted and also SLP_​A# and SLP_​LAN# asserted if applicable) during a host partition reset with power cycle or a global reset. The duration programmed in this register takes precedence over the applicable SLP_​# stretch timers in these reset scenarios.

This field is not writable when the SLP_​Sx# Stretching Policy Lock-Down bit is set.Encoding 00: 4-5sec, 01: 3-4sec, 10: 2-3 sec, 11: 1-2 sec

Note that the duration programmed in this register should never be smaller than the stretch duration programmed in the following registers -

- GEN_​PMCON_​3.SLP_​S3_​MIN_​ASST_​WDTH

- GEN_​PMCON_​3.S4MAW

- PM_​CFG.SLP_​A_​MIN_​ASST_​WDTH

- PM_​CFG.SLP_​LAN_​MIN_​ASST_​WDTH

7:6

0h

RW

T37 Value (T37_​VAL)

This field determines the delay from ungating the CPU RTC clock until the PMC considers the clock to be valid, allowing the boot flow to proceed.

Encodings:

00 - 10ms

01 - 5ms

10 - 1ms

11 - 200us

5:3

0h

RO

Reserved

2

0h

RW/L

Energy Reporting Enable (ER_​EN)

When this bit is 1, the processor will periodically calculate and report its energy consumption. When this bit is 0, the processor will neither calculate nor report its energy consumption.

1:0

0h

RW/V

Timing t581 (TIMING_​T581)

This field configures the timing involved in the power down flow (CPUPWRGD inactive to ICC_​ICLK_​INIT inactive). Encodings (all min timings):

00: 10 us (default)

01: 100 us

10: 1 ms

11: 10 ms