General Interrupt Status Register (GEN_INT_STS) – Offset fed00020 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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General Interrupt Status Register (GEN_INT_STS) – Offset fed00020

Bit Range	Default	Access	Field Name and Description
62:8	-	-	Reserved
7	0b	RW/1C	Timer 7 Interrupt Active (T07_INT_STS) Same functionality as Timer 0.
6	0b	RW/1C	Timer 6 Interrupt Active (T06_INT_STS) Same functionality as Timer 0.
5	0b	RW/1C	Timer 5 Interrupt Active (T05_INT_STS) Same functionality as Timer 0.
4	0b	RW/1C	Timer 4 Interrupt Active (T04_INT_STS) Same functionality as Timer 0.
3	0b	RW/1C	Timer 3 Interrupt Active (T03_INT_STS) Same functionality as Timer 0.
2	0b	RW/1C	Timer 2 Interrupt Active (T02_INT_STS) Same functionality as Timer 0.
1	0b	RW/1C	Timer 1 Interrupt Active (T01_INT_STS) Same functionality as Timer 0.
0	0b	RW/1C	Timer 0 Interrupt Active (T00_INT_STS) The functionality of this bit depends on whether the edge or level-triggered mode is used for this timer.(default = 0) If set to level-triggered mode:This bit will be set by hardware if the corresponding timer interrupt is active. Once the bit is set, it can be cleared by software writing a 1 to the same bit position. Writes of 0 to this bit will have noeffect. If set to edge-triggered mode: This bit should be ignored by software. Software should always write 0 to this bit. NOTE: Defaults to 0. In edge triggered mode, this bit will always read as 0 and writes will have noeffect.

Main Counter Value (MAIN_CNTR)

General Config Register (GEN_CFG) Main Counter Value (MAIN_CNTR)