Wall Clock Counter (WALCLK) – Offset 30 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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Wall Clock Counter (WALCLK) – Offset 30

The 32 bit monotonic counter provides a 'wall clock' that can be used by system software to synchronize independent audio controllers.

Bit Range	Default	Access	Field Name and Description
31:0	00000000h	RO/V	Wall Clock Counter (WALCLK) 32 bit counter that is incremented on each link BCLK period and rolls over from FFFF_FFFFh to 0000_0000h. This counter will roll over to zero with a period of approximately 179 seconds. This counter is enabled while the BCLK bit is set to 1. Software uses this counter to synchronize between multiple controllers. Will be reset on controller reset. With the introduction of multiple link segments for the Intel HD Audio controller, and the capability of running each link segment at different clock speed, the BCLK definition for this counter is fixed at 24 MHz equivalent rate always, independent of the physical link clock speed, and reports the link 0 wall clock value.

Bit Range

Default

Access

Field Name and Description

31:0

00000000h

RO/V

Wall Clock Counter (WALCLK)

32 bit counter that is incremented on each link BCLK period and rolls over from

FFFF_FFFFh to 0000_0000h. This counter will roll over to zero with a period of

approximately 179 seconds.

This counter is enabled while the BCLK bit is set to 1. Software uses this counter

to synchronize between multiple controllers. Will be reset on controller reset.

With the introduction of multiple link segments for the Intel HD Audio controller,

and the capability of running each link segment at different clock speed, the BCLK

definition for this counter is fixed at 24 MHz equivalent rate always, independent

of the physical link clock speed, and reports the link 0 wall clock value.

Stream Synchronization (SSYNC)

Interrupt Status (INTSTS) Stream Synchronization (SSYNC)