Strap Configuration 1 (STRPFUSECFG1) – Offset 200 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Introduction
8254 Timer
Advanced Programmable Interrupt Controller (APIC)
APIC Indirect
CNVi PCI Configuration
DCI PCR
- DCI Control (ECTRL)
EMMC Additional
EMMC Memory Mapped
EMMC PCI Configuration
eMMC PCR
- Dynamic Clock Gating Control (GPPRVRW1)
Enhanced SPI (eSPI) PCI Configuration
eSPI PCR
FIA Configuration PCR
GbE Configuration
GbE Memory Mapped I/O
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Generic SPI (GSPI) DMA Controller
Generic SPI (GSPI) Memory Mapped
GPIO Community 0
GPIO Community 1
GPIO Community 2
GPIO Community 3
GPIO Community 4
GSPI PCI Configuration
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High Definition Audio (D31:F3) PCI Configuration
HPET Memory Mapped
I2C Additional
I2C DMA Controller
I2C Memory Mapped
I2C PCI Congifuration
IDE Redirect PCI Configuration (D22:F2)
Integrated Clock (ICC) Configuration
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Intel RST for PCIe Storage (Remapping) PCI Configuration (D24:F0)
Intel RST for PCIe Storage MMIO
Intel(R) Management Engine Interface PCI Configuration
Intel(R) MEI MMIO
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Interrupt
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IO Trap
ISH
ISH PCH Configuration
ISH PCR
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Keyboard and Text (KT) PCI Configuration (D22:F3)
LPC Configuration
LPC PCR
- General Control And Function Disable (GCFD)
OPI PCR
P2SB PCI Configuration
PCI Express* Port Configuration
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PMC Memory Mapped
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Processor Interface Memory
PSF1
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PSF4
PSF5
RTC Indexed
RTC PCR
SATA ABAR
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SATA MXTBA
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SDXC Additional Memory Mapped
SDXC Memory Mapped
SDXC PCI Configuration
SMBus Configuration
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SPI Configuration
SPI Memory Mapped
Thermal Reporting Configuration
Thermal Reporting Memory Mapped
UART Additional Memory Mapped
UART DMA Controller
UART Memory Mapped
UART PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration
xHCI Configuration
xHCI Memory Mapped

Strap Configuration 1 (STRPFUSECFG1) – Offset 200

Bit Range	Default	Access	Field Name and Description
31	0b	RO/V	GbE Over PCI Express Port Enable Strap (GBE_PCIE_PEN) 0 : GbE MAC/PHY port communication is not enabled over PCI Express. 1 : The PCI Express port will be used for GbE MAC/PHY over PCI Express communication. Note: This field is only applicable if GbE is supported, otherwise this will be RO Reserved bit.
30:28	000b	RO/V	GBE PCIe Port Select Strap (GBE_PCIEPORTSEL) Used to determine which PCIe port to be used for GbE MAC/PHY over PCI Express communication. 000: Port 3. 001: Port 4. 010: Port 5. 011: Port 9. 100: Port 10. Others: Reserved.
27:24	-	-	Reserved
23:8	0000h	RO/V	PCIe/SATA Combo Port Select Polarity (PSCPSP) 0: When the Combo Port Select pin is '0, PCIe mode is selected. When the Combo Port Select pin is '1, SATA mode is selected. 1: When the Combo Port Select pin is '0, SATA mode is selected. When the Combo Port Select pin is '1, PCIe mode is selected. This field is expected to be set to '1 when the combo port is mapped to M.2 or SATAe connector and set to '0 when the combo port is mapped to mSATA connector.
7:2	-	-	Reserved
1	0b	RO/V	Core Dynamic Clock Gating Disable (CDCGDIS) 0: Core dynamic clock gating enabled. 1: Core dynamic clock gating disabled. This affects clock gating in SATA, DMI, PCIe, PMC, Audio, LAN, and SMBUS.
0	0b	RO/V	HSIO Power Gating Disabled (MPGD) 0b: HSIO power gating capability is enabled. 1b: HSIO power gating capability is disabled.

HSIO Lane Owner Status 1 (LOS1)

Device Reference Clock Request Mapping 3 (DRCRM3) HSIO Lane Owner Status 1 (LOS1)