Device Control (DEVIDLE_CONTROL) – Offset 24c - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Introduction
8254 Timer
Advanced Programmable Interrupt Controller (APIC)
APIC Indirect
CNVi PCI Configuration
DCI PCR
- DCI Control (ECTRL)
EMMC Additional
EMMC Memory Mapped
EMMC PCI Configuration
eMMC PCR
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- DEVIDLE Control (HECI1_DEVIDLEC)
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ISH
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UART Additional Memory Mapped
UART DMA Controller
UART Memory Mapped
UART PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration
xHCI Configuration
xHCI Memory Mapped

Device Control (DEVIDLE_CONTROL) – Offset 24c

Bit Range	Default	Access	Field Name and Description
30:5	-	-	Reserved
4	0h	RO	Interrupt Request Capable (intr_req_capable) Set to 1 by HW if it is capable of generating an interrupt on command completion, else 0.
3	1h	RW/1C	Restore Required (restore_required) When set (by HW), SW must restore state to the controller. The state may have been lost due to a reset or full power lost. SW clears the bit by writing a 1. This bit will be set on initial power up. Note: If SW is setting bit 3 together with any other bit of this register, only bit 3 is written; SW is required to do 2 writes in this case : bit 3 first and all other bits second.
2	0h	RW	Device Idle (DEVIDLE) SW sets this bit to ‘1’ to move the function into the DevIdle state. Writing this bit to ‘0’ will return the function to the fully active D0 state.
1	-	-	Reserved
0	0h	RO	Command In Progress (cmd_in_progress) HW sets this bit on a 1->0 or 0->1 transition of DEVIDLE. While set, the other bits in this register are not valid and it is illegal for SW to write to any bit in this register. HW clears this bit upon completing the DevIdle transition command. When clear, all the other bits in the register are valid and SW may write to any bit. If Interrupt Request (IR) was set for the current command, HW may clear this bit before the interrupt has been made visible to SW, since when SW actually handles a particular interrupt is not visible to the HW. SW writes to this bit have no effect.

Capabilities (CAPABLITIES)

Remap Address High (REMAP_ADDR_HI) Capabilities (CAPABLITIES)