I/O Base and Limit; Secondary Status (IOBL_SSTS) – Offset 1c - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

I/O Base and Limit; Secondary Status (IOBL_SSTS) – Offset 1c

Bit Range	Default	Access	Field Name and Description
31	0b	RW/1C/V	Detected Parity Error (DPE) Set when the port receives a poisoned TLP.
30	0b	RW/1C/V	Received System Error (RSE) Set when the port receives an ERR_FATAL or ERR_NONFATAL message from the device.
29	0b	RW/1C/V	Received Master Abort (RMA) Set when the port receives a completion with DUnsupported Request status from the device.
28	0b	RW/1C/V	Received Target Abort (RTA) Set when the port receives a completion with DCompletion Abort status from the device.
27	0b	RW/1C/V	Signaled Target Abort (STA) Set when the port generates a completion with DCompletion Abort status to the device.
26:25	00b	RO/V	Secondary DEVSEL# Timing Status (SDTS) Reserved per PCI-Express spec For PCI Bus Emulation Mode compatibility, if the PCIBEM register is set, this register returns a value of 01b when read, else this register returns a value of 00b.
24	0b	RW/1C/V	Data Parity Error Detected (DPD) Set when the BCTRL.PERE, and either of the following two conditions occurs: Port receives completion marked poisoned. Port poisons a write request to the secondary side.
23	0b	RO/V	Secondary Fast Back to Back Capable (SFBC) Reserved per PCI Express spec For PCI Bus Emulation Mode compatibility, if the PCIBEM register is set, this register returns a value of 1b when read, else this register returns a value of 0b.
22	-	-	Reserved
21	0b	RO	Secondary 66 MHz Capable (SC66) Reserved per PCI Express spec
20:16	-	-	Reserved
15:12	0h	RW	I/O Address Limit (IOLA) I/O Base bits corresponding to address lines 15:12 for 4KB alignment. Bits 11:0 are assumed to be padded to FFFh.
11:8	0h	RO	I/O Limit Address Capability (IOLC) Indicates that the bridge does not support 32-bit I/O addressing.
7:4	0h	RW	I/O Base Address (IOBA) I/O Base bits corresponding to address lines 15:12 for 4KB alignment. Bits 11:0 are assumed to be padded to 000h.
3:0	0h	RO	I/O Base Address Capability (IOBC) Indicates that the bridge does not support 32-bit I/O addressing.