JTAG and TAP Signal AC Specifications

T# Parameter	Min.	Max.	Unit	Figure	Notes_{1, 2}
TCK Frequency.		100	MHz
TCK Output Pulse Width.	5		ns	Figure: JTAG/Tap and Processor Sideband Signals High/Low Pulse Widths and Rise/ Fall Times
T1,T2: TDI, TDO, TMS Pulse Width.	1		TCK
T1,T2: TCKs required.	2		TCK
T1,T2: BPM_N[7:0] Input Pulse Width.	5		ns
T1,T2: BPM_N[7:0] Output Pulse Width.	10		ns
T3, T4: PREQ_N Rise/Fall Time (VIL to VIH).		15	ns
T5: BCLK0 to BPM_N [7:0] Output Valid Delay.	1	8.6	ns	Figure: BCLK to JTAG/TAP Signals Output Valid Delays
T5: BCLK0 to PRDY_N Output Valid Delay.	N/A	5	ns
T5: TCK to TDO Output Valid Delay.		5	ns		4
Ts: TDI, TMS Setup Time.	6.5		ns	Figure: JTAG/TAP Input Valid Delay Timing Waveform	3
Th: TDI, TMS Hold Time.	6.5		ns	Figure: JTAG/TAP Input Valid Delay Timing Waveform	3
Boundary scan all non test input setup (PREQ_N).	15		ns		6, 7
Boundary scan all non test input hold (PREQ_N).	15		ns		6, 7
*Notes:* Unless otherwise noted, all specifications in this table apply to all processor frequencies. Not 100% tested. Specified by design characterization. Referenced to the rising edge of TCK. Assuming minimum edge rate of 0.5 V/ns. Referenced to the falling edge of TCK at the processor pad. Referenced to the falling edge of TCK. Referenced to the rising edge of TCK.

SMBus Signal AC Specifications Serial VID (SVID) Interface AC Timing Specifications