Eagle Stream Platform
Data Sheet
| ID | Date | Version | Classification |
|---|---|---|---|
| 814095 | 04/04/2025 | 001 | Public |
Processor Signaling
System Memory Interface Signal Groups
PCI Express Signals
DMI3/PCI Express Signals
Intel Ultra Path Interconnect (Intel UPI)
Platform Environmental Control Interface (PECI)
System Reference Clocks (BCLK{0/1/2/3}_DP, BCLK{0/1/2/3}_DN)
JTAG and Test Access Port (TAP) Signals
Processor Sideband Signals
Power, Ground and Sense Signals
Reserved or Unused Signals
Signal DC Specifications
DDR5 Signal DC Specifications
PECI DC Specifications
System Reference Clock (BCLK{0/1/2/3}) DC Specifications
XTAL_CLK DC Specifications
SMBus DC Specifications
JTAG and TAP Signals DC Specifications
Serial VID Interface (SVID) DC Specifications
Processor Asynchronous Miscellaneous I/O DC Specifications
Miscellaneous Signals DC Specifications
SBLINK DC Specifications
AC Specifications
DDR5 Signals AC Specifications
I3C SPD
System Reference Clock (BCLK {0/1/2/3}) AC Specifications
XTAL_CLK AC Specifications
SMBus Signal AC Specifications
JTAG and TAP Signal AC Specifications
Serial VID (SVID) Interface AC Timing Specifications
Processor Asynchronous Miscellaneous I/O AC Specifications
SBLINK AC Specifications
Signal Descriptions
System Memory Interface
PCI Express Based Interface Signals
DMI3 Signals
Intel UPI Signals
PECI Signal
System Reference Clock Signals
JTAG and TAP Signals
Serial VID Interface (SVID) Signals
Processor Asynchronous Sideband and Miscellaneous Signals
Processor Power and Ground Supplies
Header
DFR: Data Format Revision
PISIZE: PIROM Size
PDA: Processor Data Address
PCDA: Processor Core Data Address
PUDA: Processor Uncore Data Address
CDA: Cache Data Address
PNDA: Package Data Address
VDA: Voltage Data Address
PNDA: Part Number Data Address
TRDA: Thermal Reference Data Address
FDA: Feature Data Address
PPIN: Protected Processor Inventory Number
Overshoot/Undershoot Magnitude
Magnitude describes the maximum potential difference between a signal and its voltage reference level. For the processor, both are referenced to VSS. It is important to note that the overshoot and undershoot conditions are separate and their impact must be determined independently.