Eagle Stream Platform

Data Sheet

ID Date Version Classification
814095 04/04/2025 001 Public
Document Table of Contents
Document Table of Contents
Legal Disclaimer (DCAI) Revision History Introduction Electrical Specifications Signal Descriptions PIROM
Legal Disclaimer (DCAI)
Revision History
Introduction
Introduction Related Publications Statement of Volatility Terminology
Related Publications
Statement of Volatility
Terminology
Electrical Specifications
Electrical Specifications Integrated Voltage Regulation Processor Signaling Signal Group Summary Mixing Processors Flexible Motherboard Guidelines (FMB) Absolute Maximum and Minimum Ratings DC Specifications AC Specifications Package C-State Power Specifications Signal Quality
Integrated Voltage Regulation
Processor Signaling
Processor Signaling System Memory Interface Signal Groups PCI Express Signals DMI3/PCI Express Signals Intel Ultra Path Interconnect (Intel UPI) Platform Environmental Control Interface (PECI) System Reference Clocks (BCLK{0/1/2/3}_DP, BCLK{0/1/2/3}_DN) JTAG and Test Access Port (TAP) Signals Processor Sideband Signals Power, Ground and Sense Signals Reserved or Unused Signals
System Memory Interface Signal Groups
PCI Express Signals
DMI3/PCI Express Signals
Intel Ultra Path Interconnect (Intel UPI)
Platform Environmental Control Interface (PECI)
Platform Environmental Control Interface (PECI) Input Device Hysteresis
Input Device Hysteresis
System Reference Clocks (BCLK{0/1/2/3}_DP, BCLK{0/1/2/3}_DN)
JTAG and Test Access Port (TAP) Signals
Processor Sideband Signals
Power, Ground and Sense Signals
Power, Ground and Sense Signals Power and Ground Lands Decoupling Guidelines Voltage Identification (VID) SVID Commands SetWP Working Point Command SetVID Fast Command SetVID Slow SetVID Decay SVID Voltage Rail Addressing
Power and Ground Lands
Decoupling Guidelines
Voltage Identification (VID)
SVID Commands
SetWP Working Point Command
SetVID Fast Command
SetVID Slow
SetVID Decay
SVID Voltage Rail Addressing
Reserved or Unused Signals
Signal Group Summary
Mixing Processors
Flexible Motherboard Guidelines (FMB)
Absolute Maximum and Minimum Ratings
Absolute Maximum and Minimum Ratings Storage Conditions Specifications
Storage Conditions Specifications
DC Specifications
DC Specifications Voltage and Current Specifications Die Voltage Validation Signal DC Specifications
Voltage and Current Specifications
Die Voltage Validation
Signal DC Specifications
Signal DC Specifications DDR5 Signal DC Specifications PECI DC Specifications System Reference Clock (BCLK{0/1/2/3}) DC Specifications XTAL_CLK DC Specifications SMBus DC Specifications JTAG and TAP Signals DC Specifications Serial VID Interface (SVID) DC Specifications Processor Asynchronous Miscellaneous I/O DC Specifications Miscellaneous Signals DC Specifications SBLINK DC Specifications
DDR5 Signal DC Specifications
PECI DC Specifications
System Reference Clock (BCLK{0/1/2/3}) DC Specifications
XTAL_CLK DC Specifications
SMBus DC Specifications
JTAG and TAP Signals DC Specifications
Serial VID Interface (SVID) DC Specifications
Processor Asynchronous Miscellaneous I/O DC Specifications
Miscellaneous Signals DC Specifications
SBLINK DC Specifications
AC Specifications
AC Specifications DDR5 Signals AC Specifications I3C SPD System Reference Clock (BCLK {0/1/2/3}) AC Specifications XTAL_CLK AC Specifications SMBus Signal AC Specifications JTAG and TAP Signal AC Specifications Serial VID (SVID) Interface AC Timing Specifications Processor Asynchronous Miscellaneous I/O AC Specifications SBLINK AC Specifications
DDR5 Signals AC Specifications
I3C SPD
System Reference Clock (BCLK {0/1/2/3}) AC Specifications
XTAL_CLK AC Specifications
SMBus Signal AC Specifications
JTAG and TAP Signal AC Specifications
Serial VID (SVID) Interface AC Timing Specifications
Processor Asynchronous Miscellaneous I/O AC Specifications
SBLINK AC Specifications
Package C-State Power Specifications
Signal Quality
Signal Quality DDR Signal Quality Specifications PCIe Signal Quality Specifications Intel UPI Signal Quality Specifications Input Reference Clock Signal Quality Specifications Overshoot/Undershoot Tolerance
DDR Signal Quality Specifications
PCIe Signal Quality Specifications
Intel UPI Signal Quality Specifications
Input Reference Clock Signal Quality Specifications
Overshoot/Undershoot Tolerance
Overshoot/Undershoot Tolerance Overshoot/Undershoot Magnitude Overshoot/Undershoot Pulse Duration Reading Overshoot/Undershoot Specification Tables Determining if a System Meets the Overshoot/Undershoot Specifications
Overshoot/Undershoot Magnitude
Overshoot/Undershoot Pulse Duration
Reading Overshoot/Undershoot Specification Tables
Determining if a System Meets the Overshoot/Undershoot Specifications
Signal Descriptions
Signal Descriptions System Memory Interface PCI Express Based Interface Signals DMI3 Signals Intel UPI Signals PECI Signal System Reference Clock Signals JTAG and TAP Signals Serial VID Interface (SVID) Signals Processor Asynchronous Sideband and Miscellaneous Signals Processor Power and Ground Supplies
System Memory Interface
PCI Express Based Interface Signals
DMI3 Signals
Intel UPI Signals
PECI Signal
System Reference Clock Signals
JTAG and TAP Signals
Serial VID Interface (SVID) Signals
Processor Asynchronous Sideband and Miscellaneous Signals
Processor Power and Ground Supplies
PIROM
Processor Information ROM Scratch EEPROM PIROM and Scratch EEPROM Supported SMBus Transactions SMBus Memory Component Addressing
Processor Information ROM
Scratch EEPROM
PIROM and Scratch EEPROM Supported SMBus Transactions
SMBus Memory Component Addressing
SMBus Memory Component Addressing Managing Data in the PIROM Header Processor Data Processor Core Data Processor Uncore Data Processor Cache Data Package Data Processor Voltage Data Part Number Data Thermal Reference Data Feature Data Protected Processor Inventory Number Checksums
Managing Data in the PIROM
Header
Header DFR: Data Format Revision PISIZE: PIROM Size PDA: Processor Data Address PCDA: Processor Core Data Address PUDA: Processor Uncore Data Address CDA: Cache Data Address PNDA: Package Data Address VDA: Voltage Data Address PNDA: Part Number Data Address TRDA: Thermal Reference Data Address FDA: Feature Data Address PPIN: Protected Processor Inventory Number
DFR: Data Format Revision
PISIZE: PIROM Size
PDA: Processor Data Address
PCDA: Processor Core Data Address
PUDA: Processor Uncore Data Address
CDA: Cache Data Address
PNDA: Package Data Address
VDA: Voltage Data Address
PNDA: Part Number Data Address
TRDA: Thermal Reference Data Address
FDA: Feature Data Address
PPIN: Protected Processor Inventory Number
Processor Data
Processor Data SQNUM: S-Spec QDF Number SAMPROD: Sample/Production Processor Core Information Hyper-Threading Support SCS: System Clock Speed Segment
SQNUM: S-Spec QDF Number
SAMPROD: Sample/Production
Processor Core Information
Hyper-Threading Support
SCS: System Clock Speed
Segment
Processor Core Data
Processor Core Data CPUID: CPUID Extended Model ID MP1CF: Maximum P1 Core Frequency MP0CF: Maximum P0 Core Frequency Core Count Indicator
CPUID: CPUID
Extended Model ID
MP1CF: Maximum P1 Core Frequency
MP0CF: Maximum P0 Core Frequency
Core Count Indicator
Processor Uncore Data
Processor Uncore Data UPIL: Number of Intel UPI Links MAXUPI: Maximum Intel UPI Transfer Rate MAXPCI: Maximum PCIe Transfer Rate DDR1DPC: Maximum Intel DDR5 1 DPC DIMM Speed DDR2DPC: Maximum Intel DDR5 2 DPC DIMM Speed High Bandwidth Memory Indicator RES1: Reserved 1
UPIL: Number of Intel UPI Links
MAXUPI: Maximum Intel UPI Transfer Rate
MAXPCI: Maximum PCIe Transfer Rate
DDR1DPC: Maximum Intel DDR5 1 DPC DIMM Speed
DDR2DPC: Maximum Intel DDR5 2 DPC DIMM Speed
High Bandwidth Memory Indicator
RES1: Reserved 1
Processor Cache Data
Processor Cache Data MLC: Mid Level Cache Size LLC: Last Level Cache Size DIMM Max Capacity
MLC: Mid Level Cache Size
LLC: Last Level Cache Size
DIMM Max Capacity
Package Data
Package Data PKGT: Package Type RES2: Reserved 2
PKGT: Package Type
RES2: Reserved 2
Processor Voltage Data
Processor Voltage Data MXVCCIN: MAX VCCIN VID MNVCCIN: MIN VCCIN VID RES3: Reserved 3
MXVCCIN: MAX VCCIN VID
MNVCCIN: MIN VCCIN VID
RES3: Reserved 3
Part Number Data
Part Number Data PFN: Processor Family Number PSN: Processor SKU Number
PFN: Processor Family Number
PSN: Processor SKU Number
Thermal Reference Data
TCASE: TCASE Maximum TDP: Thermal Design Power DTSMAX: Digital Thermal Sensor Maximum PN: Pn Power Limit
TCASE: TCASE Maximum
TDP: Thermal Design Power
DTSMAX: Digital Thermal Sensor Maximum
PN: Pn Power Limit
Feature Data
Feature Data PCFF: Processor Core Feature Flags PFF: Processor Feature Flags MPSUP: Multiprocessor Support TCDC: Tap Chain Device Count STTCKS: Static Checksum RES4: Reserved 4
PCFF: Processor Core Feature Flags
PFF: Processor Feature Flags
MPSUP: Multiprocessor Support
TCDC: Tap Chain Device Count
STTCKS: Static Checksum
RES4: Reserved 4
Protected Processor Inventory Number
Protected Processor Inventory Number PPIN: Protected Processor Inventory Number RES5: Reserved 5
PPIN: Protected Processor Inventory Number
RES5: Reserved 5
Checksums

Power and Ground Lands

All lands must be connected to their respective processor power planes, while all VSS lands must be connected to the system ground plane.

For clean on-chip power distribution, processors include lands for all required voltage supplies. These are listed in the following table.

Power and Ground Lands

Power and Ground Lands Comments
VCCIN

Power input to FIVR powered by VR 14 on board.

VCCIN voltage controlled by CPU's SVID Bus signals.

VCCINFAON Power supply for the early on domains.
VCCFA_​EHV Power supply for the PCIe5, UPI IOs and all other FIVR.
VCCFA_​EHV_​FIVRA Power supply for the analog IO FIVR.
VCCD_​HV Power supply for all processor DDR5 memory controllers.
VCCVNN Power supply for the on-PKG device, CPU GPIOs for the future drop-in compatible CPU and platform GPIOs.
VCC_​3P3_​AUX Power supply for the on package devices.
HBM_​VPP Power supply for HBM_​VPP pins as a charge pump voltage for on-package HBM. For non-HBM SKUs, HBM_​VPP pins are NC Inside the package.
VSS Ground
Decoupling Guidelines