Create TCs

Intel® Ethernet Controller E810 Application Device Queues (ADQ)

Configuration Guide

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ID 609008

Date 04/03/2023

Version 2.8

The following example creates three TCs with a small number of queues for TC0 (default TC) and the remaining number of logical cores divided between TC1 and TC2 (application TC) queues. In general, two queues for TC0 and the remaining number of cores for the application TCs are sufficient.

For best performance, the number of application worker threads/processes should match with the number of queues configured for a given application-specific TC.

Traffic originating from an application with priority set to 1 is mapped to TC1, with priority 2 mapped to TC2, etc. All default traffic is mapped to TC0.

Note:The allocation of bandwidth between TCs is not guaranteed to be proportional to the number of queues assigned. By default, the bandwidth available is roughly evenly split among all TCs. If a certain minimum bandwidth is required for a particular TC, it is recommended to use rate limiting to set either maximum or minimum bandwidth limits with the TC shaper bw_rlimit parameter.

Due to resource allocation rules, the following rules apply to the number of TC queues:

For TC0: The number of queues for the default traffic class ($num_queues_tc0) must always be a power of two.

For TC1 or higher:
- If all TCs are powers of two, they can be any number.
- If the number of queues for any TC (for TC1 or above) is not a power of two, any subsequent TC must be either exactly that number or a power of two that is less than that number.

ice-1.8.x and earlier: The total number of queues from all TCs cannot be greater than the max number of logical cores in the system.

ice-1.9.x and later: The total number of queues from all TCs is increased to a max number of 256 (the number of MSI-X interrupts per PF).

The total number of TCs allowed 16.

Example:

If num_queues_TC0=2, num_queues_TC1=16, and num_queues_TC2=7, then num_queues_TC3+ must be either exactly 7 or some power of 2 less than 7 (4,2,1).

Example:

${pathtotc}/tc qdisc add dev $iface root mqprio num_tc 3 map 0 1 2 queues \ $num_queues_tc0@0 $num_queues_tc1@$num_queues_tc0 $num_queues_tc2@$((num_queues_tc0 \ + num_queues_tc1)) hw 1 mode channel

For example, if there are 96 logical cores in a system, one possible configuration is TC0 with 2 queues, TC1 with 32 queues and TC2 with 62 queues.

${pathtotc}/tc qdisc add dev $iface root mqprio num_tc 3 map 0 1 2 queues \ 2@0 32@2 62@34 hw 1 mode channel

With ice driver version 1.9.7 and later, large TCs with up to 256 queues can be used.

Example:

To create 8 TCs with 256 queues spread across all of the TCs:

${pathtotc}/tc qdisc add dev $iface root mqprio num_tc 8 map 0 1 2 3 4 5 6 7 \ 2@0 4@2 8@6 16@14 32@30 64@62 128@126 2@254 hw 1 mode channelNote:E810 network adapters with 1 and 2 ports support up to 256 queue pairs (256 MSI-X interrupts) per-PF. The maximum number of queue pairs supported by 4 and 8 port E810 adapters is limited by the number of system cores.

Parameter Definitions

Map — Priority mapping for up to 16 priorities to TCs. For example, map 0 0 0 0 1 1 1 1 sets priorities 0-3 to use tc0 and 4-7 to use tc1).

Queues — For each TC, <num queues>@<offset>. For example, queues 2@0 16@2 assigns 2 queues to tc0 at offset 0 and 16 queues to tc1 at offset 2. A maximum total number of queues for all TCs is the number of cores.

hw 1 mode channel — Channel with hardware set to 1 is a new hardware offload mode in mqprio that makes full use of the mqprio options, the TCs, the queue configurations, and the QoS parameters.