| GPP_D0 / ISH_GP0 / BK0 / SBK0 | OD | Blink BK 0: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details. |
| GPP_D1 / ISH_GP1 / BK1 / SBK1 | OD | Blink BK 1: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details. |
| GPP_D2 / ISH_GP2 / BK2 / SBK2 | OD | Blink BK 2: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details. |
| GPP_D3/ISH_GP3/BK3/SBK3 | OD | Blink BK 3: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details. |
| GPP_D4 / IMGCLKOUT0 / BK4 / SBK4 | OD | Blink BK 4: This function provides the blink (or PWM) capability. The blink/PWM frequency and duty cycle is programmable through the PWM Control register. Refer to Volume 2 for details. |
| GPP_E22 / DDPA_CTRLCLK / DNX_FORCE_RELOAD | I | Download and Execute (DnX):Intel® CSME ROM samples this pin any time ROM begins execution. This includes the following conditions: - G3 Exit.
- Sx, Moff Exit.
- Cold Reset(Host Reset with Power Cycle) Exit.
- Warm Reset(Host Reset without Power Cycle) Exit if Intel® CSME was shutdown in Warm Reset.
- 0 => No DnX; 1=> Enter DnX mode This pin must not be sampled high at the sampling time for normal operation.
|
| GPP_E0 / SATAXPCIE0 / SATAGP0 | I | SATA port 0 or PCIe port mux select : This is used to select SATA/PCIe function to support implementations like SATA Express or mSATA. |
| GPP_A12 / SATAXPCIE1 / SATAGP1 | I | SATA port 1 or PCIe port mux select : This is used to select SATA/PCIe function to support implementations like SATA Express or mSATA. |
| GPP_D0 / ISH_GP0 / BK0 / SBK0 | OD | Serial Blink SBK 0: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details. |
| GPP_D1 / ISH_GP1 / BK1 / SBK1 | OD | Serial Blink SBK 1: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details. |
| GPP_D2 / ISH_GP2 / BK2 / SBK2 | OD | Serial Blink SBK 2: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details. |
| GPP_D3/ISH_GP3/BK3/SBK3 | OD | Serial Blink SBK 3: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details. |
| GPP_D4 / IMGCLKOUT0 / BK4 / SBK4 | OD | Serial Blink SBK 4: This function provides the capability to serialize POST or other messages on the pin to a serial monitor. The Serial Blink message is programmed through the Serial Blink Command/Status and Serial Blink Data registers. Refer to Volume 2 for details. |
| GPP_B15 / TIME_SYNC0 / ISH_GP7 | I | Time Synchronization GPIO 0: Timed GPIO event for time synchronization for interfaces that do not support time synchronization natively. |
| GPP_F9 / BOOTMPC | O | Boot Media Power Control: If BOOTMPC is 0 - Powered Off. If BOOTMPC is 1 - Powered On. |
| GPP_H10/UART0_RXD/M2_SKT2_CFG0 | I | M.2 Socket 2 Configuration : This is used to select module type and main host interface. Refer to 'Socket 2 Module Configuration' table in the PCI-SIG M.2 Specification. |
| GPP_H11/UART0_TXD/M2_SKT2_CFG1 | I | M.2 Socket 2 Configuration : This is used to select module type and main host interface. Refer to 'Socket 2 Module Configuration' table in the PCI-SIG M.2 Specification. |
| GPP_H12/I2C7_SDA/UART0_RTS#/M2_SKT2_CFG2/ISH_GP6B/DEVSLP0B | I | M.2 Socket 2 Configuration : This is used to select module type and main host interface. Refer to 'Socket 2 Module Configuration' table in the PCI-SIG M.2 Specification. |
| GPP_H13/I2C7_SCL/UART0_CTS#/M2_SKT2_CFG3/ISH_GP7B/DEVSLP1B | I | M.2 Socket 2 Configuration : This is used to select module type and main host interface. Refer to 'Socket 2 Module Configuration' table in the PCI-SIG M.2 Specification. |
| MPHY_RCOMPP | I | 100 ohm (+/- 1%) connected between MPHY_RCOMPP and MPHY_RCOMPN |
| MPHY_RCOMPN | I | 100 ohm (+/- 1%) connected between MPHY_RCOMPP and MPHY_RCOMPN |
| DMI_RCOMP | I | DMI Rcomp Signal (50 ohm +/- 1% pulldown to ground) |