Testability

JTAG:

This section contains information regarding the testability signals that provides access to JTAG, run control, system control, and observation resources. JTAG (TAP) ports are compatible with the IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1 and 1149.6 Specification. JTAG Pin definitions are from IEEE Standard Test Access Port and Boundary Scan. Architecture (IEEE Std. 1149.1-2001).

Intel^® Trace Hub:

Intel^® Trace Hub is a debug architecture that unifies hardware and software system visibility. Intel^® Trace Hub is not merely intended for hardware debug or software debug, but full system debug. This includes debugging hardware and software as they interact and produce complex system behavior. Intel^® Trace Hub defines new features and also leverages some existing debug technologies to provide a complete framework for hardware and software co-debug, software development and tuning, as well as overall system performance optimization.

There are multiple destinations to receive the trace data from Intel^® Trace Hub:

• Direct Connect Interface (DCI)
  • OOB Hosting DCI
  • USB 3.2 hosting DCI.DBC
• System Memory

There are multiple trace sources planned to be supported in the platform:

• BIOS
• Intel^® CSME
• AET (Architecture Event Trace)
• Power Management Event Trace
• Windows* ETW (for driver or application)

  Acronyms

  Acronyms	Description
  IEEE	Institute of Electrical and Electronics Engineers
  I/O	Input/Output
  I/OD	Input/Output Open Drain
  JTAG	Joint Test Action Group
  DCI	Direct Connect Interface
  DbC	Debug Class Devices

  References

  Specification	Location
  IEEE Standard Test Access Port and Boundary Scan Architecture	http://standards.ieee.org/findstds/standard/1149.1-2013.html