PCH_​JTAG_​TCK

I/O

Test Clock Input (TCK): The test clock input provides the clock for the JTAG test logic.

PCH_​JTAG_​TMS

I/OD

Test Mode Select (TMS): The signal is decoded by the Test Access Port (TAP) controller to control test operations.

PCH_​JTAG_​TDI

I/OD

Test Data Input (TDI): Serial test instructions and data are received by the test logic at TDI.

PCH_​JTAG_​TDO

I/OD

Test Data Output (TDO): TDO is the serial output for test instructions and data from the test logic defined in this standard.

PCH_​JTAGX

I/O

This pin is used to support merged debug port topologies.

DBG_​PMODE

O

ITP Power Mode Indicator. This signal is used to transmit processor and PCH power/reset information to the Debugger.

I/O

I/O

I/O

I/O

O

I

O

I