Core™ Processors
Datasheet, Volume 1 of 2
Processor SKU Support Matrix
Technology | Form Factor | Ball Count | Processor |
---|---|---|---|
DDR4 | UDIMM | 288 | S |
DDR4 | SoDIMM | 260 | H/S |
DDR4 | x16 SDP (1R)1 | 96 | H |
DDR4 | x16 DDP (1R)1 | 96 | H |
DDR4 | x8 SDP (1R)1 | 78 | H |
DDR5 | SoDIMM | 262 | H/S |
DDR5 | UDIMM | 288 | S |
DDR5 | x8 SDP (1R)1 | 78 | H |
DDR5 | x16 SDP (1R)1 | 102 | H |
LPDDR4x | x32 (1R, 2R)1 | 200 | H |
LPDDR4x | x64 (1R, 2R)1 | 432 | H |
LPDDR5 | x64 (1R, 2R)1 | 496 | H |
LPDDR5 | x32 (1R, 2R)1 | 315 | H |
- Memory down of all technologies should be implemented homogeneously, which means that all DRAM devices should be from the same vendor and have the same part number. Implementing a mix of DRAM devices may cause serious signal integrity and functional issues, DDR4/DDR5 restriction is for single MC configuration, LPDDR4x/LPDDR5 restriction is for both MC configuration (all DRAMs in the system must be from same Part Number).