Global Control (GCTL) – Offset 8 - 001 - ID:831520 | Intel® Core™ Ultra 200V Series Processors SOC I/O Registers

Intel® Core™ Ultra 200V Series Processors SOC I/O Registers

ID	Date	Version	Classification
831520	09/03/2024	001	Public

Global Control (GCTL) – Offset 8

This register provides global level control of the controller and link.

Bit Range	Default	Access	Field Name and Description
31:9	0h	RO	Reserved
8	0h	RW	Accept Unsolicited Response Enable (UNSOL) If UNSOL is a 1, Unsolicited Responses from the codecs are accepted by the controller and placed into the Response Input Ring Buffer. If UNSOL is a 0, unsolicited responses are not accepted, and dropped on the floor.
7:3	0h	RO	Reserved (Preserved) (RSVD7) SW must preserve the original value when writing.
2	0h	RW	Low Power Link Enable (LPLE) Writing a 1 to this bit enable low power operation of the HD-A link whilst CRSTB = 0. In this case, CRSTB only reset the host DMA. If this bit is 0, the legacy behavior is maintained such that CRSTB = 0 will reset the entire HD-A controller including the HD-A link and host / link DMA.
1	0h	RW/1S	Flush Control (FCNTRL) Writing a 1 to this bit initiates a flush. When the flush completion is received by the controller, hardware sets the Flush Status bit and clears this Flush Control bit. Before a flush cycle is initiated, the DMA Position Buffer must be programmed with a valid memory address by software, but the DMA Position Buffer bit 0 need not be set to enable the position reporting mechanism. Also, all streams must be stopped (the associated RUN bit must be 0). When the flush is initiated, the controller will flush pipelines to memory to guarantee that the hardware is ready to transition to a D3 state. Setting this bit is not a critical step in the power state transition if the content of the FIFOs is not critical.
0	0h	RW/V	Controller Reset(b) (CRSTB) Writing a 0 to this bit causes the Intel HD Audio controller to be reset. All state machines, FIFO's and non Primary well (always on) memory mapped configuration registers (except ECAP and PCI Configuration Registers) in the controller will be reset. The Intel HD Audio link RESET# signal will be asserted and all other link signals will be driven to their 'reset' values. After the hardware has completed sequencing into the reset state, it will report a 0 in this bit. Software must read a 0 from this bit to verify that the controller is in reset. Writing a 1 to this bit causes the controller to exit its reset state and de-assert the Intel HD Audio link RESET# signal (if LCTLx.CPA = 1). Software is responsible for setting/clearing this bit such that the minimum Intel HD Audio link RESET# signal assertion pulse width specification is met. When the controller hardware is ready to begin operation, it will report a 1 in this bit. Software must read a 1 from this bit before accessing any controller registers. The CRST# bit defaults to a 0 after hardware reset, therefore software needs to write a 1 to this bit to begin operation. Note: The CORB/RIRB RUN bits and all Stream RUN bits must be verified cleared to zero before CRST# is written to 0 (asserted) in order to assure a clean re-start. When setting or clearing CRST#, software must ensure that minimum link timing requirements (minimum RESET# assertion time, etc.) are met. When CRST# is 0, indicating that the controller is in reset, writes to all Intel HD Audio memory mapped registers are ignored as if the device is not present. The only exception is the Global Control register containing the CRST# bit itself. Note that there are others non Intel HD Audio memory mapped registers like SECPOL, HfPMCC, TSOCFG, HfFUSA, SOCCI etc in BAR0 that are NOT governed by CRST# = 1 accessibility restriction. The Global Control register is writeable as a DWord, Word, or a Byte, even when CRST# is 0, if the byte enable for the byte containing the CRST# bit (Byte Enable 0) is active. If Byte Enable 0 is not active, writes to the Global Control register will be ignored when CRST# is 0. When CRST# is 0, reads to Intel HD Audio memory mapped registers will return their default value except for registers that are not reset with PLTRST# or on a D3hot -> D0 transition.