Global Reset Causes 0 (GBLRST_CAUSE0) – Offset 1924 - 001 - ID:831520 | Intel® Core™ Ultra 200V Series Processors SOC I/O Registers

Intel® Core™ Ultra 200V Series Processors SOC I/O Registers

ID	Date	Version	Classification
831520	09/03/2024	001	Public

Global Reset Causes 0 (GBLRST_CAUSE0) – Offset 1924

Bit Range	Default	Access	Field Name and Description
31	0h	RO	Reserved
30	0h	RW/1C/V	ESE Global Reset Cause (ESE_GBLRST_REQ) If bit is set to 1, the last global reset was caused by a security global reset request.
29	0h	RO	Reserved
28	0h	RW/1C/V	gpsb_link_int_err Global Reset Host Global Reset Cause (GPSB_LINK_INT_ERR) If bit is set to 1, the last global reset was caused by gpsb_link_int_err.
27	0h	RW/1C/V	base_thrm Global Reset Host Global Reset Cause (BASE_THRM) If bit is set to 1, the last global reset was caused by a thermal global reset.
26	0h	RW/1C/V	Graphics Thermal Global Reset Cause (GFX_THRM) If bit is set to 1, the last global reset was caused by graphics thermal.
25	0h	RW/1C/V	Compute Tile Thermal Global Reset Cause (COMPUTE_THRM) If bit is set to 1, the last global reset was caused by compute tile thermal.
24	0h	RW/1C/V	PMC SRAM Global Reset Cause (PMC_RF_FUSA_ERR) If bit is set to 1, the last global reset was caused by pmc_rf_fusa_err.
23	0h	RW/1C/V	PMC ROM Parity Global Reset Cause (PMC_IROM_PARITY) If bit is set to 1, the last global reset was caused by PMC ROM parity.
22	0h	RW/1C/V	PMC SRAM Global Reset Cause (PMC_SRAM_UNC_ERR) If bit is set to 1, the last global reset was caused by pmc_sram_unc_err.
21	0h	RW/1C/V	cse_hec_unc_err Global Reset Host Global Reset Cause (CSE_HEC_UNC_ERR) If bit is set to 1, the last global reset was caused by CSE HW global reset.
20	0h	RW/1C/V	ocwdt_icc Global Reset Host Global Reset Cause (OCWDT_ICC) If bit is set to 1, the last global reset was caused by ocwdt_icc.
19	0h	RW/1C/V	Over Clocking WDT Global Reset Cause (OCWDT_NOICC) If bit is set to 1, the last global reset was caused by over clocking watchdog timer expired.
18	0h	RW/1C/V	adr_gpio Global Reset Host Global Reset Cause (ADR_GPIO) If bit is set to 1, the last global reset was caused by adr_gpio.
17	0h	RW/1C/V	CSME Uncorrectable Error Global Reset Cause (ME_UNC_ERR) If bit is set to 1, the last global reset was caused a CSME uncorrectable error.
16	0h	RW/1C/V	cpu_thrm_wdt Global Reset Host Global Reset Cause (CPU_THRM_WDT) If bit is set to 1, the last global reset was caused by cpu_thrm_wdt.
15	0h	RW/1C/V	mia_ux_err Global Reset Host Global Reset Cause (MIA_UX_ERR) If bit is set to 1, the last global reset was caused by a CSME unexpected error.
14	0h	RW/1C/V	mia_uxs_err Global Reset Host Global Reset Cause (MIA_UXS_ERR) If bit is set to 1, the last global reset was caused by a CSME unexpected shutdown error.
13	0h	RW/1C/V	ISH Global Reset Cause (ISH) If bit is set to 1, the last global reset was caused by ISH.
12	0h	RW/1C/V	SYS_PWROK Global Reset Cause (SYSPWR_FLR) If bit is set to 1, the last global reset was caused by SYS_PWROK going low in S0.
11	0h	RW/1C/V	Power Failure Global Reset Cause (PCHPWR_FLR) If bit is set to 1, the last global reset was caused by PLT_PWROK going low in S0.
10	0h	RW/1C/V	PMC FW Global Reset Cause (PMC_FW) If bit is set to 1, the last global reset was caused by PCM FW.
9	0h	RW/1C/V	CSME WDT Global Reset Cause (ME_WDT) If bit is set to 1, the last global reset was caused by CSME watchdog timer expired.
8	0h	RW/1C/V	PMC WDT Global Reset Cause (PMC_WDT) If bit is set to 1, the last global reset was caused by PMC watchdog timer expired.
7	0h	RW/1C/V	lt_reset Global Reset Host Global Reset Cause (LT_RESET) If bit is set to 1, the last global reset was caused by lt_reset.
6	0h	RW/1C/V	CSME Global Reset Cause (MEGBL) If bit is set to 1, the last global reset was caused by a CSME global reset (with details reflected in GBLRST_CAUSE1 register).
5	0h	RW/1C/V	SoC North Thermal Global Reset Cause (SOCN_THRM) If bit is set to 1, the last global reset was caused by the SoC north tile thermal.
4	0h	RW/1C/V	CSME Power Button Override Global Reset Cause (ME_PBO) If bit is set to 1, the last global reset was caused by CSME power button override.
3	0h	RW/1C/V	SoC South Thermal Global Reset Cause (SOCS_THRM) If bit is set to 1, the last global reset was caused by the SoC South tile thermal.
2	0h	RW/1C/V	PMC Uncorrectable Error Global Reset Cause (PMC_UNC_ERR) If bit is set to 1, the last global reset was caused by a PMC uncorrectable error.
1	0h	RW/1C/V	Power Button Override Global Reset Cause (PBO) If bit is set to 1, the last global reset was caused by power button override.
0	0h	RW/1C/V	Security Policy Error Global Reset Cause (SECURE_POLICY_ERR) If bit is set to 1, the last global reset was caused by a security policy error.