REG SDA_HOLD_SWITCH_DLY_TIMING (SDA_HOLD_SWITCH_DLY_TIMING) – Offset 230 - 001 - ID:831520 | Intel® Core™ Ultra 200V Series Processors SOC I/O Registers

Intel® Core™ Ultra 200V Series Processors SOC I/O Registers

ID	Date	Version	Classification
831520	09/03/2024	001	Public

REG SDA_HOLD_SWITCH_DLY_TIMING (SDA_HOLD_SWITCH_DLY_TIMING) – Offset 230

SDA Hold and Mode Switch Delay Timing Register
The Bits [2:0] of this register are used to shift the sda_out with respect to sda_oe while switching
transfer from Open Drain timing to Push Pull timing. The bits [10:8] of this register are used to shift
the sda_oe with respect to sda_out while switching transfer from Pus pull timing to Open Drain
timing. The bits [18:16] of this register are used to control the hold time of SDA during transmit mode
in SDR & DDR transfers. The bits [26:24] of this register are used to control the hold time of SDA
during recive mode in SDR & DDR transfers.

Bit Range	Default	Access	Field Name and Description
31:27	0h	RO	RSVD_31_27 (RSVD_31_27) RSVD_31_27: These bits in SCL SDA Hold and Mode Switch Delay Timing Registers is reserved. It will always return 0.
26:24	0h	RW	SDA_RX_HOLD (SDA_RX_HOLD) Sets the required SDA hold time in units of core_clk period when DWC_mipi_i3c acts as a receiver.
23:19	0h	RO	RSVD_17_23 (RSVD_17_23) RSVD_17_23: These bits in SCL SDA Hold and Mode Switch Delay Timing Registers is reserved. It will always return 0.
18:16	1h	RW	SDA_TX_HOLD (SDA_TX_HOLD) This field controls the hold time (in term of the core clock period) of the transmit data (SDA) with respect to the SCL edge in SD FM FM+ SDR and DDR speed mode of operations. This field is not applicable for the ternary speed modes. The valid values are 1 to 7. Others are Reserved.
15:11	0h	RO	RSVD_11_15 (RSVD_11_15) RSVD_11_15: These bits in SCL SDA Hold and Mode Switch Delay Timing Registers is reserved. It will always return 0.
10:8	0h	RW	SDA_PP_OD_SWITCH_DLY (SDA_PP_OD_SWITCH_DLY) This field is used to delay the sda_oe with respect to sda_out (in terms of the core clock period) while switching the transfer from PP1 (Push-Pull Mode SDA=1) to OD1 (Open Drain SDA=1). The valid value can range from 0 to 4. Others are Reserved.
7:3	0h	RO	RSVD_7_3 (RSVD_7_3) RSVD_7_3: These bits in SCL SDA Hold and Mode Switch Delay Timing Registers is reserved. It will always return 0.
2:0	0h	RW	SDA_OD_PP_SWITCH_DLY (SDA_OD_PP_SWITCH_DLY) This field is used to delay the sda_out with respect to sda_oe while switching the transfer from OD1 (Open-Drain Mode SDA=1) to PP1 (Push-Pull Mode SDA=1). The valid value can range from 0 to 4. Others are reserved.