Feature Set

• 6 Neural Compute Engine Tiles detailed in the following sections
• Two 512-bit DSP Core detailed in the following sections
• DMA Engine:
  • 2x 64B AXI Interfaces to DDR
  • Bit Compactor unit for weights decompression
  • Broadcasting/Multicasting Capability to allow DMA to feed multiple NCE Tiles simultaneously
  • Prefetching capability in the DMA controller. A dedicated prefetch machine provides single read accesses to pages at a configurable offset from the current transfer.
  • Address Patching capability for DRAM Accesses

• M2I Engine:

  • Speeds up the pre-processing stage that takes place between the media pipeline output and the inference pipeline input
  • Supports a software pre-configured chain of transforms accelerated by hardware
  • Support of Cropping, Scaling, Colorspace conversion, Normalization Transforms

• 256kB of SHAVE L2 Cache for Data and Instruction shared between DSPs (ACT-SHAVE)
• Barriers for hardware and assisted task synchronization and pipelining
• Programmable HW FIFO Block for Work Descriptors and IPC
• Virtual Addressing for all resources used during Inference
  • Memory, Barriers, FIFOs and DMA/M2I Interrupt IDs