Intel® Core™ Ultra 200V Series Processors

Datasheet, Volume 1 of 2

ID Date Version Classification
829568 05/27/2025 004 Confidential
Document Table of Contents

Introduction

This document is intended for Original Equipment Manufacturers (OEMs), Original Design Manufacturers (ODM) and BIOS vendors creating products based on the Intel® Core™ Ultra 200V Series Processors.

This document assumes a working knowledge of the vocabulary and principles of interfaces and architectures such as PCI Express* (PCIe*), Universal Serial Bus (USB), eXtensible Host Controller Interface (xHCI), and so on.

This document abbreviates buses as Bn, devices as Dn and functions as Fn. For example, Device 31 Function 0 is abbreviated as D31:F0, Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will not be used, and can be considered to be Bus 0.

The Intel® Core™ Ultra 200V Series Processor is a 64-bit, multi-core processor built on Intel 4 process and N3B technology.

  • The Intel® Core™ Ultra 200V Series Processor is offered in a single package platform that includes the compute tile, the SOC tile, and LPDDR5x MOP Memory on the same package.

The following table describes the offered Intel® Core™ Ultra 200V Series Processors:

Intel® Core™ Ultra 200V Series Processor Form Factors

Form Factors1

Package

Processor Base Power

2, 3

Compute Tile

P-cores

Compute Tile

LP E cores

SOC Tile

LP cores

Graphics

Configuration

Xe2-cores

Memory Capacity [GB]

Platform Type

Fanless Clamshell or Detachable

BGA2833

8 W

4

4

0

up to 8

16 / 32

1-Chip

Fanned Thin and Light

BGA2833

17 W

4

4

0

up to 8

16 / 32

1-Chip

Notes:
  1. Form Factors offering may change.
  2. For additional Processor Base Power Configurations, refer to Processor Base Power Thermal and Power Specifications. For adjustment to the Processor Base Power it is required to preserve base frequency associated with the sustained long-term thermal capability.
  3. Processor Base Power workload does not reflect I/O connectivity cases such as Thunderbolt.
  4. 1*Xe2 = 8 execution units.
Note:

Not all processor interfaces and features are presented in all Processor Lines. The presence of various interfaces and features will be indicated within the relevant sections and tables.

Fanless Clamshell or Detachable Diagram

Fanned Thin and Light Diagram