12th Generation Intel® Core™ Processors Datasheet, Volume 1 of 2


ID 655258
Date 28/10/2021 00:00:00
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Document Table of Contents

DDR I/O Interleaving

Note:The processor supports I/O interleaving, which has the ability to swap DDR bytes for routing considerations. BIOS configures the I/O interleaving mode before DDR training.

There are two supported modes:

  • Interleave (IL)
  • Non-Interleave (NIL)

The following table and figure describe the pin mapping between the IL and NIL modes.

Interleave (IL) and Non-Interleave (NIL) Modes Pin Mapping

Channel Byte Channel Byte Channel Byte
DDR0 Byte0 DDR0 Byte0 DDR0 Byte0
DDR0 Byte1 DDR0 Byte1 DDR0 Byte1
DDR0 Byte2 DDR0 Byte4 DDR1 Byte0
DDR0 Byte3 DDR0 Byte5 DDR1 Byte1
DDR0 Byte4 DDR1 Byte0 DDR2 Byte0
DDR0 Byte5 DDR1 Byte1 DDR2 Byte1
DDR0 Byte6 DDR1 Byte4 DDR3 Byte0
DDR0 Byte7 DDR1 Byte5 DDR3 Byte1
DDR1 Byte0 DDR0 Byte2 DDR0 Byte2
DDR1 Byte1 DDR0 Byte3 DDR0 Byte3
DDR1 Byte2 DDR0 Byte6 DDR1 Byte2
DDR1 Byte3 DDR0 Byte7 DDR1 Byte3
DDR1 Byte4 DDR1 Byte2 DDR2 Byte2
DDR1 Byte5 DDR1 Byte3 DDR2 Byte3
DDR1 Byte6 DDR1 Byte6 DDR3 Byte2
DDR1 Byte7 DDR1 Byte7 DDR3 Byte3

DDR4 Interleave (IL) and Non-Interleave (NIL) Modes Mapping