12th Generation Intel® Core™ Processors Datasheet, Volume 1 of 2

Datasheet

ID Date Version Classification
655258 28/10/2021 00:00:00 Public Content

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Document Table of Contents

System Memory Timing Support

The IMC supports the following DDR Speed Bin, CAS Write Latency (CWL), and command signal mode timings on the main memory interface:

  • tCL = CAS Latency
  • tRCD = Activate Command to READ or WRITE Command delay
  • tRP = PRECHARGE Command Period
  • tRPb = per-bank PRECHARGE time
  • tRPab = all-bank PRECHARGE time
  • CWL = CAS Write Latency
  • Command Signal modes:
    • 2N indicates a new DDR5/DDR4 command may be issued every 2 clocks
    • 1N indicates a new DDR5/DDR4 command may be issued every clock.