12th Generation Intel® Core™ Processors Datasheet, Volume 1 of 2
Datasheet
ID | Date | Version | Classification |
---|---|---|---|
655258 | 28/10/2021 00:00:00 | Public Content |
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Security Technologies
Intel® Trusted Execution Technology
Intel® Advanced Encryption Standard New Instructions
Perform Carry-Less Multiplication Quad Word Instruction
Intel® Secure Key
Execute Disable Bit
Boot Guard Technology
Intel® Supervisor Mode Execution Protection
Intel® Supervisor Mode Access Protection
Intel® Secure Hash Algorithm Extensions
User Mode Instruction Prevention
Read Processor ID
Intel® Multi-Key Total Memory Encryption
Intel® Control-flow Enforcement Technology
KeyLocker Technology
Devil’s Gate Rock
Power and Performance Technologies
Intel® Smart Cache Technology
IA Cores Level 1 and Level 2 Caches
Ring Interconnect
Intel® Hybrid Technology
Intel® Turbo Boost Max Technology 3.0
Intel® Hyper-Threading Technology
Intel® Turbo Boost Technology 2.0
Enhanced Intel SpeedStep® Technology
Intel® Thermal Velocity Boost (Intel® TVB)
Intel® Speed Shift Technology
Intel® Advanced Vector Extensions 2 (Intel® AVX2)
Intel® 64 Architecture x2APIC
Intel® Dynamic Tuning Technology
Intel® GMM and Neural Network Accelerator
Cache Line Write Back
Remote Action Request
User Mode Wait Instructions
Power Management
Advanced Configuration and Power Interface (ACPI) States Supported
Processor IA Core Power Management
Processor AUX Power Management
Processor Graphics Power Management
System Agent Enhanced Intel SpeedStep® Technology
Rest Of Platform (ROP) PMIC
PCI Express* Power Management
TCSS Power State
Thermal Management Features
Adaptive Thermal Monitor
Digital Thermal Sensor
PROCHOT# Signal
PROCHOT Output Only
Bi-Directional PROCHOT#
PROCHOT Demotion Algorithm
Voltage Regulator Protection using PROCHOT#
Thermal Solution Design and PROCHOT# Behavior
Low-Power States and PROCHOT# Behavior
THRMTRIP# Signal
Critical Temperature Detection
On-Demand Mode
MSR Based On-Demand Mode
I/O Emulation-Based On-Demand Mode
System Memory Interface
Processor SKU Support Matrix
Supported Memory Modules and Devices
System Memory Timing Support
Memory Controller (MC)
Memory Controller Power Gate
System Memory Controller Organization Mode (DDR4/5 Only)
System Memory Frequency
Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
Data Scrambling
Data Swapping
DDR I/O Interleaving
DRAM Clock Generation
DRAM Reference Voltage Generation
Data Swizzling
Error Correction With Standard RAM
Post Package Repair (PPR)
Signal Description
System Memory Interface
PCI Express* Graphics (PEG) Signals
Direct Media Interface (DMI) Signals
Reset and Miscellaneous Signals
Display Interfaces
Processor Clocking Signals
Testability Signals
Error and Thermal Protection Signals
Power Sequencing Signals
Processor Power Rails
Ground and Reserved Signals
Processor Internal Pull-Up / Pull-Down Terminations
PECI Bus Architecture
The PECI architecture is based on a wired-OR bus that the clients (as processor PECI) can pull up (with the strong drive).
The idle state on the bus is ‘0’ (logical low) and near zero (Logical voltage level).
The following figures demonstrate PECI design and connectivity:
- PECI Host-Clients Connection: While the host/originator can be third party PECI host and one of the PECI client is a processor PECI device.
- PECI EC Connection.