12th Generation Intel® Core™ Processors Datasheet, Volume 1 of 2


ID 655258
Date 28/10/2021 00:00:00
Public Content

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

embedded DisplayPort* (eDP*)

The embedded DisplayPort* (eDP*) is an embedded version of the DisplayPort standard oriented towards applications such as notebook and All-In-One PCs. Like DisplayPort, embedded DisplayPort* also consists of the Main Link, Auxiliary channel, and an optional Hot-Plug Detect signal.

  • Supported on Low power optimized pipes.

  • Support up to HBR3 link rate.

  • Support Backlight PWM control and enable signals, and power enable.

  • Support VESA DSC 1.1.

  • Support SSC.

  • Panel Self Refresh 1.

  • MSO 2x2 (Multi Segment Operation).

  • Dedicated Aux channel.

  • Adaptive Sync.


S-Processor Line1


4096x2304 60 Hz 36 bpp

5120x3200 60 Hz 24 bpp

eDP* with DSC5

5120x3200 120 Hz 30 bpp

  1. Maximum resolution is based on the implementation of 4 lanes at HBR3 link data rate.
  2. bpp - bit per pixel.
  3. Resolution support is subject to memory BW availability.
  4. High resolution panels supporting Display Stream Compression (DSC) are supported, technology enablement may be limited due to low market availability.