12th Generation Intel® Core™ Processors Datasheet, Volume 1 of 2


ID 655258
Date 28/10/2021 00:00:00
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Document Table of Contents

Package C-States and Display Resolutions

The integrated graphics engine has the frame buffer located in system memory. When the display is updated, the graphics engine fetches display data from system memory. Different screen resolutions and refresh rates have different memory latency requirements. These requirements may limit the deepest Package C-state the processor can enter. Other elements that may affect the deepest Package C-state available are the following:

  • Display is on or off
  • Single or multiple displays
  • Native or non-native resolution
  • Panel Self Refresh (PSR) technology

Note:Display resolution is not the only factor influencing the deepest Package C-state the processor can get into. Device latencies, interrupt response latencies, and core C-states are among other factors that influence the final package C-state the processor can enter.

The following table lists display resolutions and deepest available package C-State.The display resolutions are examples using common values for blanking and pixel rate. Actual results will vary. The table shows the deepest possible Package C-state.System workload, system idle, and AC or DC power also affect the deepest possible Package C-state.

Deepest Package C-State Available

S 8+8 Processor line


Number of Displays

PSR Enabled

PSR Disabled

Up to 5120x3200 60Hz3




  1. All Deep states are with Display ON.
  2. The deepest C-state has variance, dependent various parameters such SW and Platform devices.
  3. Partial data based on Pre-Silicon estimation.