13th Generation Intel® Core™ and Intel® Core™ 14th Generation Processors
Datasheet, Volume 1 of 2
Supporting 13th Generation Intel® Core™ Processor for S, H, P, HX, and U Processor Line Platforms, formerly known as Raptor Lake, Intel® Core™ 14th Generation Processor for S, HX, and U Processor Line Platform, formerly known as Raptor Lake Refresh and Intel® Xeon™ E 2400 Processor, formerly known As Raptor Lake–E
DDR5 Memory Interface
| Signal Name | Description | Dir. | Buffer Type | Link Type | Availability |
|---|---|---|---|---|---|
| DDR0_DQ0[7:0] DDR0_DQ1[7:0] DDR0_DQ2[7:0] DDR0_DQ3[7:0] DDR0_DQ4[7:0] DDR1_DQ0[7:0] DDR1_DQ1[7:0] DDR1_DQ2[7:0] DDR1_DQ3[7:0] DDR1_DQ4[7:0] DDR2_DQ0[7:0] DDR2_DQ1[7:0] DDR2_DQ2[7:0] DDR2_DQ3[7:0] DDR2_DQ4[3:0] DDR3_DQ0[7:0] DDR3_DQ1[7:0] DDR3_DQ2[7:0] DDR3_DQ3[7:0] DDR3_DQ4[3:0] | Data Buses: Data signals interface to the SDRAM data buses. Example: DDR0_DQ2[5] refers to DDR channel 0, Byte 2, Bit 5. | I/O | DDR5 | SE | S |
| DDR0_DQSP[4:0] DDR0_DQSN[4:0] DDR1_DQSP[4:0] DDR1_DQSN[4:0] DDR2_DQSP[4:0] DDR2_DQSN[4:0] DDR3_DQSP[4:0] DDR3_DQSN[4:0] | Data Strobes: Differential data strobe pairs. The data is captured at the crossing point of DQS during reading and write transactions. Example: DDR0_DQSP0 refers to DQSP of DDR channel 0, Byte 0. | I/O | DDR5 | Diff | S |
| DDR0_CLKN[3:0] DDR0_CLKP[3:0] DDR1_CLKN[3:0] DDR1_CLKP[3:0] DDR2_CLKN[3:0] DDR2_CLKP[3:0] DDR3_CLKN[3:0] DDR3_CLKP[3:0] | SDRAM Differential Clock: Differential clocks signal pairs, pair per rank. The crossing of the positive edge and the negative edge of their complement are used to sample the command and control signals on the SDRAM. | O | DDR5 | Diff | S |
| DDR0_CS[3:0] DDR1_CS[3:0] DDR2_CS[3:0] DDR3_CS[3:0] | Chip Select: (1 per rank). These signals are used to select particular SDRAM components during the active state. There is one Chip Select for each SDRAM rank. The Chip select signal is Active Low. | O | DDR5 | SE | S |
| DDR0_CA[12:0] DDR1_CA[12:0] DDR2_CA[12:0] DDR3_CA[12:0] | Command Address: These signals are used to provide the multiplexed command and address to the SDRAM. | O | DDR5 | SE | S |
| DDR_VREF_CA[3:0] | Memory Reference Voltage for Command and Address | O | A | SE | S |
| DDR0_VREF_CA0 DDR1_VREF_CA0 | Memory Reference Voltage for Command and Address | O | A | SE | H/P/U |
| DDR_VTT_CTL | System Memory Power Gate Control: When signal is high – platform memory VTT regulator is enable, output high. When signal is low - Disables the platform memory VTT regulator in C8 and deeper and S3. | O | A | SE | S |
| DDR0_ALERT# DDR1_ALERT# | Alert: This signal is used at command training only. It is getting the Command and Address Parity error flag during training. CRC feature is not supported. | I | DDR5 | SE | S |