PCI Express* Root Port Support Feature Details

Intel® Core™ Ultra 200S, Intel® Core™ Ultra 200S Plus ,Intel® Core™ Ultra 200HX and 200HX Plus Series Processors

Datasheet, Volume 1 of 2

ID	Date	Version	Classification
832586	03/17/2026		Public

PCI Express* Root Port Feature Details

Product	Max Transfer Rate	Max Devices (Root Ports)	Max Lanes	PCIe Gen Type	Encoding	Transfer Rate (MT/s)	Theoretical Max Bandwidth (GB/s)
							x1	x2	x4	x8	x16
Processor	32 GT/s (Gen5)	5	24 ²	1	8b/10b	2500	0.25	0.50	1.00	2.00	4.00
				2	8b/10b	5000	0.50	1.00	2.00	4.00	8.00
				3	128b/130b	8000	1.00	2.00	3.94	7.88	15.75
				4	128b/130b	16000	1.97	3.94	7.88	15.75	31.51
				5	128b/130b	32000	3.94	7.88	15.75	31.51	63.02
Notes: Theoretical Maximum Bandwidth (GB/s) = ((Transfer Rate * Encoding * # PCIe Lanes) /8)/1000 Gen5 with 16 PCIe Lanes Example = ((32000 * 128/130 * 16)/8)/1000 = 63.02 GB/s Maximum of 20 PCIe Lanes support up to Gen5 transfer rate (16 SOC-S + 4 IOE)

Supported PCI Express* Link Configurations

Notes:

Covers all the Processor PCIe Controller hardware supported PCIe Bifurcation Configurations. Refer to the processor SKU breakdowns for SKU specific supported PCIe Bifurcation Configurations

Device (BDF) groupings have multiple functions, the lowest active Root Port within the Device (BDF) grouping will always be assigned Function 0 while any remaining active Root Port within the Device (BDF) grouping will be assigned their mapped Function # as shown.

Reduced Root Port width configurations, within Bi-Furcation configurations, are supported (example: x2 PCIe End Point Device populated in a PCIe Controller set as 1px4/1px16 will result in a 1px2 PCIe Root Port configuration or x1 PCIe End Point Device populated in a PCIe Controller set as 1px4/1px16 will result in a 1px1 PCIe Root Port configuration).
FIA = Flex-IO Adapter

The PCIe* Link Configuration support will vary depending on the SKU. Refer to the SKU details covered in the Introduction.

LR = Lane Reversal

PCIe Configuration (#p) x (#) = (Number of PCIe Root Ports) x (Number of Data Lane Pairs per PCIe Root Port)

RP# refers to a specific PCI Express* Root Port #; for example RP3 = PCI Express* Root Port 3

A PCIe* Lane is composed of a single pair of Transmit (TX) and Receive (RX) differential pairs. A connection between two PCIe* devices is known as a PCIe* Link, and is built up from a collection of one or more PCIe* Lanes which make up the width of the link (such as bundling 2 PCIe* Lanes together would make a x2 PCIe* Link). A PCIe* Link is addressed by the lowest number PCIe* Lane it connects to and is known as the PCIe* Root Port (such as a x2 PCIe* Link connected to PCIe* Lanes 3 and 4 would be called x2 PCIe* Root Port 3).

The PCIe* Lanes can be configured independently from one another but the max number of configured Root Ports (Devices) must not be exceeded

Unidentified lanes within a PCIe* Link Configuration are disabled but their physical lanes are used for the identified Root Port

PCIe Controller Bifurcation/Configuration Mode Strap Details

Notes:

The SOC Tile x16 Gen5 PCIe Controller Bifurcation modes, for PCIe Lanes 1 to 16, are configured based off Pin Strap and Soft Strap settings. The Pin Strap settings are done with the GPP_SA[16:15] signal pins where motherboard designs may implement them using board switches, jumpers, or through pull-ups and pull-downs. Both of these Pin Straps and Soft Straps must be set to match the motherboard implementation for the SOC Tile x16 Gen5 PCIe Controller Bifurcation.
One has to understand the impact of these SOC Tile strap configuration settings between the SOC GPP_SA[16:15] Pin Straps and the SOC Soft Straps. Incorrect or mismatched settings could result in a Root Port and link not training to the expected data width or an end point device not getting detected.
- If the GPP_SA Pin Straps and the Soft Straps do not match then the one with the lowest data width strap value between the two will have priority and set the bi-furcation for the associated PCIe Controller Root Port.
- If the GPP_SA Pin Straps and the Soft Straps both match then the data width value from them results in the same priority and sets the bi-furcation for the associated PCIe Controller Root Port.
- The Soft Straps set the Lane Reversal (LR) for the associated PCIe Controller Root Port.
- Examples:
- Case1: GPP_SA [16:15] = 10b (2px8) and Soft Straps = 1x16 --> Results in 2px8 Root Port Configuration
- Case2: GPP_SA [16:15] = 10b (2px8) and Soft Straps = 1x16 LR --> Results in 1px8 LR + 1px8 LR Root Port Configuration
- Case3: GPP_SA [16:15] = 00b (1px16) and Soft Straps = 2x8 --> Results in 2px8 Root Port Configuration
- Case4: GPP_SA [16:15] = 11b (1px8 + 1px4 + 1px4) and Soft Straps = 1x8 LR, 1x8 LR --> Results in 1px8 LR + 1px4 LR + 1px4 LR Root Port Configuration
The IOE Tile PCIe Gen4 and Gen5 x4 Controller configuration modes are set only through the IOE Soft Straps.