13th Generation Intel® Core™ Processors
Datasheet, Volume 1 of 2
Supporting 13th Generation Intel® Core™ Processor for S Processor Line Platforms, formerly known as Raptor Lake
Power Sequencing Signals
Signal Name | Description | Dir. | Buffer Type | Link Type | Availability |
---|---|---|---|---|---|
PROCPWRGD | Processor Power Good: The processor requires this input signal to be a clean indication that the VCC1P05V_PROC and VDD2 power supplies are stable and within specifications. This requirement applies regardless of the S-state of the processor. 'Clean' implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal should then transition monotonically to a high state. | I | CMOS | SE | All Processor Lines |
VCCST_PWRGD | VCCST Power Good: The processor requires this input signal to be a clean indication that the VCC1P05_PROC and VDD2 power supplies are stable and within specifications. This signal should have a valid level during both S0 and S3 power states. 'Clean' implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal then transition monotonically to a high state. | I | CMOS | SE | All Processor Lines |
VCCST_PWRGD_SX | VCCST_PWRGD_SX: the processor required this input signal to be a clean indicator that there is a Sx state, the net will be dropped in Sx, the signal will support IO during. | I | CMOS | SE | All Processor Lines |
SKTOCC# | Socket Occupied: Pulled down directly (0 Ohms) on the processor package to the ground. There is no connection to the processor silicon for this signal. System board designers may use this signal to determine if the processor is present. | N/A | N/A | SE | S Processor Line |
VIDSOUT | VIDSOUT, VIDSCK, VIDALERT#: These signals comprise a three-signal serial synchronous interface used to transfer power management information between the processor and the voltage regulator controllers. | I/O | I:GTL/O:OD | SE | All Processor Lines |
VIDSCK | O | OD | |||
VIDALERT# | I | CMOS | |||
PM_SYNC | Power Management Sync: A sideband signal to communicate power management status from the PCH to the processor. PCH report EXTTS#/EVENT# status to the processor. | I | CMOS | SE | S-Processor Line |
PM_DOWN | Power Management Down: Sideband to PCH. Indicates processor wake up event EXTTS# on PCH. The processor combines the pin status into the OLTM/CLTM. | O | CMOS | SE | S-Processor Line |