13th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2
Supporting 13th Generation Intel® Core™ Processor for S Processor Line Platforms, formerly known as Raptor Lake

ID 743844
Date 10/13/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

Intel® Virtualization Technology for Directed I/O

Intel® VT-d Objectives

The key Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) objectives are domain-based isolation and hardware-based virtualization. A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated. Intel® VT-d provides accelerated I/O performance for a Virtualization platform and provides software with the following capabilities:

  • I/O Device Assignment and Security: for flexibly assigning I/O devices to VMs and extending the protection and isolation properties of VMs for I/O operations.
  • DMA Remapping: for supporting independent address translations for Direct Memory Accesses (DMA) from devices.
  • Interrupt Remapping: for supporting isolation and routing of interrupts from devices and external interrupt controllers to appropriate VMs.
  • Reliability: for recording and reporting to system software DMA and interrupt errors that may otherwise corrupt memory or impact VM isolation.

Intel® VT-d accomplishes address translation by associating transaction from a given I/O device to a translation table associated with the Guest to which the device is assigned. It does this by means of the data structure in the following illustration. This table creates an association between the device's PCI Express* Bus/Device/Function (B/D/F) number and the base address of a translation table. This data structure is populated by a VMM to map devices to translation tables in accordance with the device assignment restrictions above and to include a multi-level translation table (VT-d Table) that contains Guest specific address translations.

Device to Domain Mapping Structures

Intel® VT-d functionality often referred to as an Intel® VT-d Engine, has typically been implemented at or near a PCI Express* host bridge component of a computer system. This might be in a chipset component or in the PCI Express functionality of a processor with integrated I/O. When one such VT-d engine receives a PCI Express transaction from a PCI Express bus, it uses the B/D/F number associated with the transaction to search for an Intel® VT-d translation table. In doing so, it uses the B/D/F number to traverse the data structure shown in the above figure. If it finds a valid Intel® VT-d table in this data structure, it uses that table to translate the address provided on the PCI Express bus. If it does not find a valid translation table for a given translation, this results in an Intel® VT-d fault. If Intel® VT-d translation is required, the Intel® VT-d engine performs an N-level table walk.

For more information, refer to Intel® Virtualization Technology for Directed I/O Architecture Specification http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf

Intel® VT-d Key Features

The processor supports the following Intel® VT-d features:

  • Memory controller and processor graphics comply with the Intel® VT-d 2.1 Specification.
  • Two Intel® VT-d DMA remap engines.
    • iGFX DMA remap engine
    • Default DMA remap engine (covers all devices except iGFX)
  • Support for root entry, context entry, and the default context
  • 46-bit guest physical address and host physical address widths
  • Support for 4K page sizes only
  • Support for register-based fault recording only (for single entry only) and support for MSI interrupts for faults
  • Support for both leaf and non-leaf caching
  • Support for boot protection of default page table
  • Support for non-caching of invalid page table entries
  • Support for hardware-based flushing of translated but pending writes and pending reads, on IOTLB invalidation
  • Support for Global, Domain-specific and Page specific IOTLB invalidation
  • MSI cycles (MemWr to address FEEx_​xxxxh) not translated.
  • Interrupt Remapping is supported
  • Queued invalidation is supported
  • Intel® VT-d translation bypass address range is supported (Pass Through)

The processor supports the following added new Intel® VT-d features:

  • 4-level Intel® VT-d Page walk – both default Intel® VT-d engine, as well as the Processor Graphics VT-d engine are upgraded to support 4-level Intel® VT-d tables (adjusted guest address width of 48 bits)
  • Intel® VT-d super-page – support of Intel® VT-d super-page (2 MB, 1 GB) for default Intel® VT-d engine (that covers all devices except IGD)

    IGD Intel® VT-d engine does not support super-page and BIOS should disable super-page in default Intel® VT-d engine when iGfx is enabled.

Note:Intel® VT-d Technology may not be available on all SKUs.