13th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2
Supporting 13th Generation Intel® Core™ Processor for S Processor Line Platforms, formerly known as Raptor Lake

ID 743844
Date 10/13/2022

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Document Table of Contents

Memory Controller (MC)

The integrated memory controller is responsible for transferring data between the processor and the DRAM as well as the DRAM maintenance. There are two instances of MC, one per memory slice. Each controller is capable of supporting up to two channels of DDR5 and one channel of DDR4.

The two controllers are independent and have no means of communicating with each other, they need to be configured separately.

In a symmetric memory population, each controller only view half of the total physical memory address space.

Both MC support only one technology in a system, DDR4 or DDR5. Mix of technologies in one system is not allowed.