13th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2
Supporting 13th Generation Intel® Core™ Processor for S/P/PX/H/HX/U Processor Line Platforms, formerly known as Raptor Lake

ID 743844
Date 01/06/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

Processor Power Rails

Power Rail

Description

S-Processor Line Controls

HX-Processor Line Controls

P/PX/H/U Processor Lines Controls

VccCORE

Processor IA Cores Power Rail

SVID

SVID

SVID

VccGT

Graphic Power Rail

SVID

SVID

SVID

VccIN_​AUX3

Support internal FIVR’s 1, SA, PCIe, Display IO and other internal Blocks.

PCH VID

PCH VID

PCH VID

Vcc1P05_​PROC4

Sustain and Sustain Gated Power Rail

Fixed

Fixed

Fixed

Vcc1p8_​PROC

PCIE PHY Power 1.8V Rail

Fixed

Fixed

Fixed

VccMIPILP DDI PHY power rail for MIPI DSI interface ------ ------ Fixed

VDD2

Integrated Memory

Controller Power Rail

Fixed (Memory technology dependent)

Fixed (Memory technology dependent)

Fixed (Memory technology dependent)

Notes:
  1. FIVR = Fully Integrated Voltage Regulator. For details, refer to Voltage Regulator.
  2. VccIN_​AUX has a few discrete voltages defined by PCH VID.
  3. VCC1P05_​PROC, for S processor the power rail is connected to a platform voltage regulator to supply power to the sustaining power rails.

  4. VccMIPILP: When MIPI DSI interface is been used, this power rail should be connected to 1.24V rail.
  5. VCC1P05_​PROC for P-Processor line power rail is connected to VCC1P05_​OUT_​FET rail through a power gate at platform, to supply power to the sustain gated power rails.