13th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2
Supporting 13th Generation Intel® Core™ Processor for S/P/PX/H/HX/U Processor Line Platforms, formerly known as Raptor Lake

ID Date Version Classification
743844 01/06/2023 Public

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Document Table of Contents

Processor Power Rails

Processor Power Rails Signals 

Signal Name

Description

Dir.

Buffer Type

Link

Type

Availability

VCCCORE

Processor IA Cores and Ring power rail

I

PWR

All Processor Lines

VCCGT

Processor Graphics power rail

I

PWR

All Processor Lines

VCCIN_​AUX

Support internal FIVR’s, SA, PCIe, Display IO and other internal Blocks.

I

PWR

All Processor Lines

VCCIN_​AUX_​FLTR

Support internal FIVR’s, SA, PCIe, Display IO and other internal Blocks.

this pin should be connected to decoupling for filter.

I

PWR

All Processor Lines

VCC1P05_​PROC

Sustain and Sustain Gated Power Rail

I

PWR

All Processor Lines

VCC1P8_​PROC

PCIE PHY Power 1.8V Rail

I

PWR

S Processor Line

P Processor Line

VDD2

System Memory power rail

I

PWR

All Processor Lines

VDD2_​EDGECAP

Internal power pin, this pin should be connected to a decoupling capacitor and ground

I

PWR

S Processor Line

VCCIN_​AUX_​EDGECAP

Internal power pin, this pin should be connected to a decoupling capacitor and ground

I

PWR

S Processor Line

VDD2_​DDR5_​SENSE Isolated, low impedance DDR5 voltage sense pins.

N/A

PWR_​ SENSE

S Processor Line

VCCGT_​SENSE

Isolated, low impedance voltage sense pins. They can be used to sense or measure voltage near the silicon.

N/A

PWR_​ SENSE

All Processor Lines

VCC_​SENSE

All Processor Lines

VCCIN_​AUX_​SENSE / VCCINAUX_​SENSE

All Processor Lines

VCC1P05_​PROC_​SENSE

S Processor Line

VCC1P05_​PROC_​OUT

VCC1P05_​PROC_​OUT is the power provider to the balls AR14 and AT12, so those three balls should be connected at board level.

O PWR

P Processor Line

U Processor Line

VCC_​DISPIO DDI PHY power rail (Shorted on package): Note:When no MIPI DSI interface is been used (only eDP), VCC_​DISPIO should be shorted with VCC1P05_​PROC_​OUT, VCC_​MIPILP can be left N.C. Note:When MIPI DSI interface is been used, VCC_​MIPILP should be connected to 1.24v (on board VR), VCC_​DISPIO can be left N.C. I PWR

P Processor Line

U Processor Line

VCC_​MIPILP I PWR

P Processor Line

U Processor Line

Processor Ground Rails Signals 

Signal Name

Description

Dir.

Buffer Type

Link

Type

Availability

VSSGT_​SENSE

Isolated, low impedance Ground sense pins. They can be used for the reference ground near the silicon.

N/A

GND_​

SENSE

All Processor Lines

VSS_​SENSE

All Processor Lines

VSSIN_​AUX_​SENSE / VSSINAUX_​SENSE

All Processor Lines