BPM#[3:0]

Breakpoint and Performance Monitor Signals: Outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance.

I/O

GTL

SE

S Processor Line

P Processor Line

U Processor Line

PROC_​PRDY#

Probe Mode Ready: PROC_​PRDY# is a processor output used by debug tools to determine processor debug readiness.

O

OD

SE

S Processor Line

P Processor Line

U Processor Line

PROC_​PREQ#

Probe Mode Request: PROC_​PREQ# is used by debug tools to request debug operation of the processor.

I

GTL

SE

S Processor Line

P Processor Line

U Processor Line

PROC_​TCK

Test Clock: This signal provides the clock input for the processor Test Bus (also known as the Test Access Port). This signal should be driven low or allowed to float during power on Reset.

I

GTL

SE

S Processor Line

PROC_​TDI

Test Data In: This signal transfers serial test data into the processor. This signal provides the serial input needed for JTAG specification support.

I

GTL

SE

S Processor Line

PROC_​TDO

Test Data Out: This signal transfers serial test data out of the processor. This signal provides the serial output needed for JTAG specification support.

O

OD

SE

S Processor Line

PROC_​TMS

Test Mode Select: A JTAG specification support signal used by debug tools.

I

GTL

SE

S Processor Line

PROC_​JTAG_​TCK

Test Clock: This signal provides the clock input for the processor Test Bus (also known as the Test Access Port). This signal should be driven low or allowed to float during power on Reset.

I

GTL

SE

P Processor Line

PROC_​JTAG_​TDI

Test Data In: This signal transfers serial test data into the processor. This signal provides the serial input needed for JTAG specification support.

I

GTL

SE

P Processor Line

PROC_​JTAG_​TDO

Test Data Out: This signal transfers serial test data out of the processor. This signal provides the serial output needed for JTAG specification support.

O

OD

SE

P Processor Line

PROC_​JTAG_​TMS

Test Mode Select: A JTAG specification support signal used by debug tools.

I

GTL

SE

P Processor Line

PROC_​JTAG_​TRST#

Test Reset: Resets the Test Access Port (TAP) logic. This signal should be driven low during power on Reset. Refer to the appropriate processor Debug Port Design Guide for complete implementation details.

I

GTL

SE

S Processor Line

P Processor Line

DBG_​PMODE

Processor debug mode

O

GTL

SE

P Processor Line