13th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2
Supporting 13th Generation Intel® Core™ Processor for S/P/PX/H/HX/U Processor Line Platforms, formerly known as Raptor Lake

ID Date Version Classification
743844 01/06/2023 Public

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Document Table of Contents

VccGT DC Specifications

Processor Graphics (VccGT) Supply DC Voltage and Current Specifications

Symbol

Parameter

Segment

Minimum

Typical

Maximum

Unit

Note1

Operating voltage

Active voltage Range for VccGT

All Processor Lines

0

1.5

V

2, 3, 6, 8,11

IccMAX_​GT (S-Processors)

Max. Current for Processor Graphics Rail

S-Processor Line

(125W)

30

A

6

IccMAX_​GT (S-Processors)

Max. Current for Processor Graphics Rail

S-Processor Line

(65W)

30

A

6

IccMAX_​GT (S-Processors)

Max. Current for Processor Graphics Rail

S-Processor Line

(35W)

30

A

6

IccMAX_​GT (HX Processors)

Max. Current for Processor Graphics Rail

HX Processor Line

(55W)

30

A

6

IccMAX_​GT (H-Processors)

Max. Current for Processor Graphics Rail

H-Processor Line

(45W)

55

A

6

IccMAX_​GT (P-Processors)

Max. Current for Processor Graphics Rail

P-Processor Line

(28W)

55

A

6

IccMAX_​GT (PX- Processors)

Max. Current for Processor Graphics Rail

PX-Processor Line

(45W)

55

A

6

IccMAX_​GT (U- Processors)

Max. Current for Processor Graphics Rail

U-Processor Line

(15W)

40

A

6

IccTDC_​GT

Thermal Design Current (TDC) for Processor Graphics Rail

S-Processor Line

(125W)

22

A

6

IccTDC_​GT

Thermal Design Current (TDC) for Processor Graphics Rail

S-Processor Line

(65W)

22

A

6

IccTDC_​GT

Thermal Design Current (TDC) for Processor Graphics Rail

S-Processor Line

(35W)

22/20

A

6

IccTDC_​GT

Thermal Design Current (TDC) for Processor Graphics Rail

HX Processor Line

(55W)

22

A

6

IccTDC_​GT

Thermal Design Current (TDC) for Processor Graphics Rail

H-Processor Line

(45W)

35

A

6

IccTDC_​GT

Thermal Design Current (TDC) for Processor Graphics Rail

P-Processor Line

(28W)

35

A

6

IccTDC_​GT

Thermal Design Current (TDC) for Processor Graphics Rail

PX-Processor Line

(45W)

35

A

6

IccTDC_​GT

Thermal Design Current (TDC) for Processor Graphics Rail

U-Processor Line

(15W)

23

A

6

TOBVCCGT

Voltage Tolerance

PS0, PS1 ,PS2, PS3

±20

mV

3,4

TOBVCCGT+Ripple

Ripple Tolerance

PS0, PS1, PS2, PS3

-35 /+50

mV

3, 4,13

DC_​LL ( S Processors)

DC Loadline

S -Processor Line

4.0

7, 9, 10

DC_​LL ( HX Processors)

DC Loadline

HX -Processor Line

4.0

7, 9, 10

DC_​LL (PX Processors)

DC Loadline

PX-Processor Line

3.2

7, 9, 10

DC_​LL (U/P/H Processors)

DC Loadline

U/P/H -Processor Line

3.2

7, 9, 10

AC_​LL (S Processors)

AC Loadline

S -Processor Line

4.0

7, 9, 10

AC_​LL (HX Processors)

AC Loadline

HX -Processor Line

  • Below 300KHz: 4.0
  • 300KHz-1MHz: linear decrease with log(frequency) from 4.0 to 3.0
  • Above 1MHz: 3.0

7, 9, 10

AC_​LL (PX Processors)

AC Loadline

PX-Processor Line

3.2

7, 9, 10

AC_​LL (U/P/H Processors)

AC Loadline

U/P/H -Processor Line

  • Below 400kHz: 3.2
  • 400kHz-2MHz: linear decrease with log (frequency) from 3.2 to 2.4
  • Above 2MHz: 2.4

7, 9, 10,12

T_​OVS_​MAX

Max Overshoot time

10

µs

V_​OVS_​MAX

Max Overshoot

70

mV

Notes:
  1. All specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date.
  2. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. This differs from the VID employed by the processor during a power or thermal management event (Intel Adaptive Thermal Monitor, Enhanced Intel® SpeedStep Technology, or low-power states).
  3. PSx refers to the voltage regulator power state as set by the SVID protocol.
  4. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. This differs from the VID employed by the processor during a power or thermal management event (Intel Adaptive Thermal Monitor, Enhanced Intel® SpeedStep Technology, or low-power states).
  5. Operating voltage range in steady state.
  6. Load Line measured at the sense point.
  7. An IMVP9.1 controller to support VCCGT need to have an offset voltage capability and potentially VCCGT output voltage (VID+Offset) may be higher than 1.5V
  8. Ripple can be higher if DC TOB is below 20mV, as long as Total TOB is within -35mV/+50mV.