REG DATA_BUFFER_THLD_CTRL (DATA_BUFFER_THLD_CTRL) – Offset d4 - 001 - ID:831520 | Intel® Core™ Ultra 200V Series Processors SOC I/O Registers

Intel® Core™ Ultra 200V Series Processors SOC I/O Registers

ID	Date	Version	Classification
831520	09/03/2024	001	Public

REG DATA_BUFFER_THLD_CTRL (DATA_BUFFER_THLD_CTRL) – Offset d4

Data Buffer Threshold Control Register used to control thresholds that are triggering
interrupts on specific thresholds of Command, Response, Rx or Tx Data Buffer Queues.

Bit Range	Default	Access	Field Name and Description
31:28	0h	RO	RSVD_31_28 (RSVD_31_28) RSVD_31_28: These bits in Data Buffer Threshold Control Register are reserved. It will always return 0.
27	0h	RO	RSVD_27 (RSVD_27) RSVD_27: This bit in Data Buffer Threshold Control Register are reserved. It will always return 0.
26:24	1h	RW	RX_START_THLD (RX_START_THLD) Receive Start Threshold Value. When the controller is set up to initiate a read transfer, it waits until the programmed number of empty locations(or more) are available in its receive buffer before it initiates the read transfer on the I3C Interface.
23:20	0h	RO	RSVD_23_20 (RSVD_23_20) RSVD_23_20: These bits in Data Buffer Threshold Control Register are reserved. It will always return 0.
19	0h	RO	RSVD_19 (RSVD_19) RSVD_19: This bit in Data Buffer Threshold Control Register are reserved. It will always return 0.
18:16	1h	RW	TX_START_THLD (TX_START_THLD) Transfer Start Threshold Value. When the controller is set up to initiate a write transfer, it waits until the programmed number of entries (or more) are available in its transmit buffer before it initiates the write transfer on the I3C Interface.
15:12	0h	RO	RSVD_15_12 (RSVD_15_12) RSVD_15_12: These bits in Data Buffer Threshold Control Register are reserved. It will always return 0.
11	0h	RO	RSVD_11 (RSVD_11) RSVD_11: This bit in Data Buffer Threshold Control Register are reserved. It will always return 0.
10:8	4h	RW	RX_BUF_THLD (RX_BUF_THLD) Receive Buffer Threshold Value. Controls the number of entries (or above) in the Receive FIFO that trigger the RX_THLD_STAT interrupt.
7:4	0h	RO	RSVD_7_4 (RSVD_7_4) RSVD_7_4: These bits in Data Buffer Threshold Control Register are reserved. It will always return 0.
3	0h	RO	RSVD_3 (RSVD_3) This bit in Data Buffer Threshold Control Register are reserved. It will always return 0.
2:0	4h	RW	TX_BUF_THLD (TX_BUF_THLD) Transmit Buffer Threshold Value. Controls the number of empty locations (or above) in the Transmit FIFO that trigger the TX_THLD_STAT interrupt.