12th Generation Intel® Core™ Processors

Datasheet, Volume 1 of 2

ID 655258
Date 05/30/2022

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Document Table of Contents

embedded DisplayPort* (eDP*)

The embedded DisplayPort* (eDP*) is an embedded version of the DisplayPort standard oriented towards applications such as notebook and All-In-One PCs. Like DisplayPort, embedded DisplayPort* also consists of the Main Link, Auxiliary channel, and an optional Hot-Plug Detect signal.

  • Supported on Low power optimized pipes.

  • Support up to HBR3 link rate.

  • Support Backlight PWM control and enable signals, and power enable.

  • Support VESA DSC 1.1.

  • Support SSC.

  • Panel Self Refresh 1.

  • Panel Self Refresh 2 (supported on P/H/U processor lines).

  • MSO 2x2 (Multi Segment Operation).

  • Dedicated Aux channel.

  • Adaptive Sync.

Embedded DisplayPort Maximum Resolution


S/HX-Processor Line1

H/P-Processor Line

U-Processor Line


4096x2304 60 Hz 36 bpp

5120x3200 60 Hz 24 bpp

4096x2304 60Hz 36bpp

5120x3200 60Hz 24bpp

4096x2304 60Hz 36bpp

5120x3200 60Hz 24bpp

eDP* with DSC5

5120x3200 120 Hz 30 bpp

5120x3200 120Hz 30bpp

5120x3200 120Hz 30bpp

  1. Maximum resolution is based on the implementation of 4 lanes at HBR3 link data rate.
  2. PSR2 supported for H/P/U processor lines only and up to 5 K resolutions.
  3. bpp - bit per pixel.
  4. Resolution support is subject to memory BW availability.
  5. High resolution panels supporting Display Stream Compression (DSC) are supported, technology enablement may be limited due to low market availability.