12th Generation Intel® Core™ Processors
Datasheet, Volume 1 of 2
Legal Disclaimer Revision History Introduction Technologies Power Management Thermal Management Memory USB-C* Sub System PCIe* Interface Direct Media Interface and On Package Interface Graphics Display Camera/MIPI Signal Description Electrical Specifications Package Mechanical Specifications CPU And Device IDs
Security Technologies Intel® Trusted Execution Technology Intel® Advanced Encryption Standard New Instructions Perform Carry-Less Multiplication Quad Word Instruction Intel® Secure Key Execute Disable Bit Boot Guard Technology Intel® Supervisor Mode Execution Protection Intel® Supervisor Mode Access Protection Intel® Secure Hash Algorithm Extensions User Mode Instruction Prevention Read Processor ID Intel® Multi-Key Total Memory Encryption Intel® Control-flow Enforcement Technology KeyLocker Technology Devil’s Gate Rock
Power and Performance Technologies Intel® Smart Cache Technology IA Cores Level 1 and Level 2 Caches Ring Interconnect Intel® Performance Hybrid Architecture Intel® Turbo Boost Max Technology 3.0 Intel® Hyper-Threading Technology Intel® Turbo Boost Technology 2.0 Enhanced Intel SpeedStep® Technology Intel® Thermal Velocity Boost (Intel® TVB) Intel® Speed Shift Technology Intel® Advanced Vector Extensions 2 (Intel® AVX2) Intel® 64 Architecture x2APIC Intel® Dynamic Tuning Technology Intel® GMM and Neural Network Accelerator Cache Line Write Back Remote Action Request User Mode Wait Instructions
Power Management Advanced Configuration and Power Interface (ACPI) States Supported Processor IA Core Power Management Processor AUX Power Management Processor Graphics Power Management System Agent Enhanced Intel SpeedStep® Technology Rest Of Platform (ROP) PMIC PCI Express* Power Management TCSS Power State
Thermal Management Features Adaptive Thermal Monitor Digital Thermal Sensor PROCHOT# Signal PROCHOT Output Only Bi-Directional PROCHOT# PROCHOT Demotion Algorithm Voltage Regulator Protection using PROCHOT# Thermal Solution Design and PROCHOT# Behavior Low-Power States and PROCHOT# Behavior THRMTRIP# Signal Critical Temperature Detection On-Demand Mode MSR Based On-Demand Mode I/O Emulation-Based On-Demand Mode
System Memory Interface Processor SKU Support Matrix Supported Memory Modules and Devices System Memory Timing Support Memory Controller (MC) Memory Controller Power Gate System Memory Controller Organization Mode (DDR4/5 Only) System Memory Frequency Technology Enhancements of Intel® Fast Memory Access (Intel® FMA) Data Scrambling Data Swapping LPDDR5 Ascending and Descending LPDDR4x CMD Mirroring DDR I/O Interleaving DRAM Clock Generation DRAM Reference Voltage Generation Data Swizzling Error Correction With Standard RAM Post Package Repair (PPR)
Signal Description System Memory Interface PCI Express* Graphics (PEG) Signals Direct Media Interface (DMI) Signals Reset and Miscellaneous Signals Display Interfaces USB Type-C Signals MIPI* CSI-2 Interface Signals Processor Clocking Signals Testability Signals Error and Thermal Protection Signals Power Sequencing Signals Processor Power Rails Ground and Reserved Signals Processor Internal Pull-Up / Pull-Down Terminations
Processor Interfaces DC Specifications DDR4 DC Specifications DDR5 DC Specifications LPDDR4x DC Specification LPDDR5 DC Specification PCI Express* Graphics (PEG) Group DC Specifications Digital Display Interface (DDI) DC Specifications CMOS DC Specifications GTL and OD DC Specification PECI DC Characteristics
Intel® Smart Cache Technology
The Intel® Smart Cache Technology is a shared Last Level Cache (LLC).
- The LLC is non-inclusive.
- The LLC may also be referred to as a 3rd level cache.
- The LLC is shared between all IA cores as well as the Processor Graphics.
- For P Cores The 1st and 2nd level caches are not shared between physical cores and each physical core has a separate set of caches.
- For E Cores The 1st level cache is not shared between physical cores and each physical core has a separate set of caches.
- For E Cores The 2nd level cache is shared between 4 physical cores.
- The size of the LLC is SKU specific with a maximum of 3MB per P physical core or 4 E cores and is a 12-way associative cache.