General Purpose Event 1 Status [63:32] (GPE1_STS_95_64) – Offset 18 - 001 - ID:831520 | Intel® Core™ Ultra 200V Series Processors SOC I/O Registers

Intel® Core™ Ultra 200V Series Processors SOC I/O Registers

ID	Date	Version	Classification
831520	09/03/2024	001	Public

General Purpose Event 1 Status [63:32] (GPE1_STS_95_64) – Offset 18

Note: This register is symmetrical to the General Purpose Event 0 Enable [127:96] Register. Unless indicated otherwise below, if the corresponding _EN bit is set, then when the STS bit get set, the processor will generate a Wake Event. Once back in an S0 state (or if already in an S0 state when the event occurs), the processor will also generate an SCI if the SCIEN bit is set, or an SMI# if the SCIEN bit is not set and GBL_SMI_EN is set.
Note that GPE0_STS bits 95:0 are claimed by the GPIO register block.

Bit Range	Default	Access	Field Name and Description
31:14	0h	RO	Reserved
13	0h	RW/1C/V	TC_TBT1 PCI Express Status (TC_TBT1_PCI_EXP_STS) This bit will be set to 1 by hardware to indicate that: The PME event message was received on TC_TBT1 PCI-Express Ports An Assert PMEGPE message received from the MCH via DMI Note: The PCI WAKE# pin and the PCI-Express Beacons have no impact on this bit. Software attempts to clear this bit by writing a 1 to this bit position. If the TC_TBT1_PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the leveltriggered SCI will remain active. Note that a race condition exists where the PCI Express device sends another PME message because the PCI Express device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express specification. The window for this race condition is approximately 95-105 milliseconds.
12	0h	RW/1C/V	TC_TBT0 PCI Express Status (TC_TBT0_PCI_EXP_STS) This bit will be set to 1 by hardware to indicate that: The PME event message was received on TC_TBT0 PCI-Express Ports An Assert PMEGPE message received from the MCH via DMI Note: The PCI WAKE# pin and the PCI-Express Beacons have no impact on this bit. Software attempts to clear this bit by writing a 1 to this bit position. If the TC_TBT0_PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the leveltriggered SCI will remain active. Note that a race condition exists where the PCI Express device sends another PME message because the PCI Express device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express specification. The window for this race condition is approximately 95-105 milliseconds.
11	0h	RW/1C/V	TC_PCIE3 PCI Express Status (TC_PCIE3_PCI_EXP_STS) This bit will be set to 1 by hardware to indicate that: The PME event message was received on TC_PCIE3 PCI-Express Ports An Assert PMEGPE message received from the MCH via DMI Note: The PCI WAKE# pin and the PCI-Express Beacons have no impact on this bit. Software attempts to clear this bit by writing a 1 to this bit position. If the TC_PCIE3_PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the leveltriggered SCI will remain active. Note that a race condition exists where the PCI Express device sends another PME message because the PCI Express device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express specification. The window for this race condition is approximately 95-105 milliseconds.
10	0h	RW/1C/V	TC_PCIE2 PCI Express Status (TC_PCIE2_PCI_EXP_STS) This bit will be set to 1 by hardware to indicate that: The PME event message was received on TC_PCIE2 PCI-Express Ports An Assert PMEGPE message received from the MCH via DMI Note: The PCI WAKE# pin and the PCI-Express Beacons have no impact on this bit. Software attempts to clear this bit by writing a 1 to this bit position. If the TC_PCIE2_PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the leveltriggered SCI will remain active. Note that a race condition exists where the PCI Express device sends another PME message because the PCI Express device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express specification. The window for this race condition is approximately 95-105 milliseconds.
9	0h	RW/1C/V	TC_PCIE1 PCI Express Status (TC_PCIE1_PCI_EXP_STS) This bit will be set to 1 by hardware to indicate that: The PME event message was received on TC_PCIE1 PCI-Express Ports An Assert PMEGPE message received from the MCH via DMI Note: The PCI WAKE# pin and the PCI-Express Beacons have no impact on this bit. Software attempts to clear this bit by writing a 1 to this bit position. If the TC_PCIE1_PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the leveltriggered SCI will remain active. Note that a race condition exists where the PCI Express device sends another PME message because the PCI Express device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express specification. The window for this race condition is approximately 95-105 milliseconds.
8	0h	RW/1C/V	TC_PCIE0 PCI Express Status (TC_PCIE0_PCI_EXP_STS) This bit will be set to 1 by hardware to indicate that: The PME event message was received on TC_PCIE0 PCI-Express Ports An Assert PMEGPE message received from the MCH via DMI Note: The PCI WAKE# pin and the PCI-Express Beacons have no impact on this bit. Software attempts to clear this bit by writing a 1 to this bit position. If the TC_PCIE0_PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the leveltriggered SCI will remain active. Note that a race condition exists where the PCI Express device sends another PME message because the PCI Express device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express specification. The window for this race condition is approximately 95-105 milliseconds.
7	0h	RW/1C/V	IOE PCI Express Status (IOE_PCI_EXP_STS) This bit will be set to 1 by hardware to indicate that: - The PME event message was received on IOE PCI-Express Ports - An Assert PMEGPE message received from the processor Note: The PCI WAKE# pin and the PCI-Express Beacons have no impact on this bit. Software attempts to clear this bit by writing a 1 to this bit position. If the SPE_PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the leveltriggered SCI will remain active. Note that a race condition exists where the PCI Express device sends another PME message because the PCI Express device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express specification. The window for this race condition is approximately 95-105 milliseconds.
6:2	0h	RO	Reserved
1	0h	RW/1C/V	SPB PCI Express Status (SPB_PCI_EXP_STS) This bit will be set to 1 by hardware to indicate that: - The PME event message was received on SPB PCI-Express Ports - An Assert PMEGPE message received from the processor Note: The PCI WAKE# pin and the PCI-Express Beacons have no impact on this bit. Software attempts to clear this bit by writing a 1 to this bit position. If the SPB_PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the leveltriggered SCI will remain active. Note that a race condition exists where the PCI Express device sends another PME message because the PCI Express device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express specification. The window for this race condition is approximately 95-105 milliseconds.
0	0h	RW/1C/V	SPA PCI Express Status (SPA_PCI_EXP_STS) This bit will be set to 1 by hardware to indicate that: - The PME event message was received on SPA PCI-Express Ports - An Assert PMEGPE message received from the processor Note: The PCI WAKE# pin and the PCI-Express Beacons have no impact on this bit. Software attempts to clear this bit by writing a 1 to this bit position. If the SPA_PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the leveltriggered SCI will remain active. Note that a race condition exists where the PCI Express device sends another PME message because the PCI Express device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express specification. The window for this race condition is approximately 95-105 milliseconds.