Intel® Core™ Ultra 200V Series Processors SOC I/O Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 831520 | 09/03/2024 | 001 | Public |
Introduction
8254 Timer I/O
ACE MMIO
ACE PCI Configuration
Advanced Programmable Interrupt (APIC) Index
Advanced Programmable Interrupt (APIC) Mem
CNVi WiFi* PCI Configuration
eSPI PCI Configuration (D31:F0)
eSPI PCR
GPIO Community 0
GPIO Community 1
GPIO Community 3
GPIO Community 4
GPIO Community 5
GSPI Additional MMIO
GSPI DMA Controller
GSPI MMIO
GSPI PCI Configuration (D30:F2/3, D18:F6)
High Precision Event Timer (HPET) MMIO
I2C Additional MMIO
I2C DMA Controller
I2C MMIO
I2C PCI Configuration (D21:F0/1/2/3; D25:F0/1
I3C Additional MMIO
I3C DMA Controller
I3C MMIO
I3C PCI Configuration (D17:F0/2)
IDE Redirection (IDE-R) PCI Configuration (D22:F2)
Integrated GbE Configuration (D31:F6)
Integrated GbE Memory Mapped I/O
Intel® Management Interface (MEI) Memory Mapped I/O
Intel® Management Interface (MEI) PCI Configuration
Intel® Trace Hub PCI Configuration (D31:F7)
Intel® Trusted Execution Technology Configuration Registers
Intergrated Sensor Hub (ISH) PCI Configuration (D18:F0)
Interrupt I/O
Interrupt PCR
IO Trap
IOM Register
Keyboard and Text (KT) Redirection PCI Configuration (D22:F3)
p2sb cfg
PCI Express* (PCIe*) Congifuration (D28:F0/1/2/3/4/5/6/7)
PMC I/O Based
PMC MMIO
PMC PCI Configuration (D31:F2)
Processor I/O
PSF6
RTC I/O
RTC Index
RTC PCR
Shared SRAM PCI Configuration (D20:F2)
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration (D31:F5)
TCSS IOM AON
TCSS IOM MAIN
TCSS xHCI PCI Configuration (D13:F0)
Touch Host Controller (THC) MMIO Common
Touch Host Controller (THC) MMIO Port
Touch Host Controller (THC) PCI Configuration (D16:F0/1)
TPM Configuration
UART Additional MMIO
UART DMA Controller
UART MMIO
UART PCI Configuration (D30:F0/1, D25:F2)
UFS PCI Configuration (D18:F7)
xHCI MMIO
xHCI PCI Configuration (D20:F0)
8254 Timer I/O
Counter 0_Interval Timer Status Byte Format Register (C0_ITSBFR)
Counter 0_Counter Access Ports Register (C0_CAPR)
Counter 2_Interval Timer Status Byte Format Register (C2_ITSBFR)
Counter 2_Counter Access Ports Register (C2_CAPR)
Timer Control Word Register (TCW)
Read Back Command (RBC)
Counter Latch Command (CLC)
ACE MMIO
Global Capabilities (GCAP)
Minor Version (VMIN)
Major Version (VMAJ)
Output Payload Capability (OUTPAY)
Global Control (GCTL)
Wake Enable (WAKEEN)
Wake Status (WAKESTS)
Global Status (GSTS)
Global Capabilities 2 (GCAP2)
Linked List Capabilities Header (LLCH)
Input Stream Payload Capability (INSTRMPAY)
Interrupt Control (INTCTL)
Interrupt Status (INTSTS)
Wall Clock Counter (WALCLK)
Stream Synchronization (SSYNC)
CORB Lower Base Address (CORBLBASE)
CORB Upper Base Address (CORBUBASE)
CORB Write Pointer (CORBWP)
CORB Read Pointer (CORBRP)
CORB Control (CORBCTL)
CORB Status (CORBSTS)
CORB Size (CORBSIZE)
RIRB Lower Base Address (RIRBLBASE)
RIRB Upper Base Address (RIRBUBASE)
RIRB Write Pointer (RIRBWP)
Response Interrupt Count (RINTCNT)
RIRB Control (RIRBCTL)
RIRB Status (RIRBSTS)
RIRB Size (RIRBSIZE)
Immediate Response (IR)
DMA Position Lower Base Address (DPLBASE)
DMA Position Upper Base Address (DPUBASE)
Input Stream Descriptor x Control (ISD0CTL_B0)
Input Stream Descriptor x Control (ISD0CTL_B2)
Input Stream Descriptor x Status (ISD0STS)
Input Stream Descriptor x Link Position in Buffer (ISD0LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD0CBL)
Input Stream Descriptor x Last Valid Index (ISD0LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD0FIFOW)
Input Stream Descriptor x FIFO Size (ISD0FIFOS)
Input Stream Descriptor x Format (ISD0FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD0BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD0BDLPUBA)
Input Stream Descriptor x Control (ISD1CTL_B0)
Input Stream Descriptor x Control (ISD1CTL_B2)
Input Stream Descriptor x Status (ISD1STS)
Input Stream Descriptor x Link Position in Buffer (ISD1LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD1CBL)
Input Stream Descriptor x Last Valid Index (ISD1LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD1FIFOW)
Input Stream Descriptor x FIFO Size (ISD1FIFOS)
Input Stream Descriptor x Format (ISD1FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD1BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD1BDLPUBA)
Input Stream Descriptor x Control (ISD2CTL_B0)
Input Stream Descriptor x Control (ISD2CTL_B2)
Input Stream Descriptor x Status (ISD2STS)
Input Stream Descriptor x Link Position in Buffer (ISD2LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD2CBL)
Input Stream Descriptor x Last Valid Index (ISD2LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD2FIFOW)
Input Stream Descriptor x FIFO Size (ISD2FIFOS)
Input Stream Descriptor x Format (ISD2FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD2BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD2BDLPUBA)
Input Stream Descriptor x Control (ISD3CTL_B0)
Input Stream Descriptor x Control (ISD3CTL_B2)
Input Stream Descriptor x Status (ISD3STS)
Input Stream Descriptor x Link Position in Buffer (ISD3LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD3CBL)
Input Stream Descriptor x Last Valid Index (ISD3LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD3FIFOW)
Input Stream Descriptor x FIFO Size (ISD3FIFOS)
Input Stream Descriptor x Format (ISD3FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD3BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD3BDLPUBA)
Input Stream Descriptor x Control (ISD4CTL_B0)
Input Stream Descriptor x Control (ISD4CTL_B2)
Input Stream Descriptor x Status (ISD4STS)
Input Stream Descriptor x Link Position in Buffer (ISD4LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD4CBL)
Input Stream Descriptor x Last Valid Index (ISD4LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD4FIFOW)
Input Stream Descriptor x FIFO Size (ISD4FIFOS)
Input Stream Descriptor x Format (ISD4FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD4BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD4BDLPUBA)
Input Stream Descriptor x Control (ISD5CTL_B0)
Input Stream Descriptor x Control (ISD5CTL_B2)
Input Stream Descriptor x Status (ISD5STS)
Input Stream Descriptor x Link Position in Buffer (ISD5LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD5CBL)
Input Stream Descriptor x Last Valid Index (ISD5LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD5FIFOW)
Input Stream Descriptor x FIFO Size (ISD5FIFOS)
Input Stream Descriptor x Format (ISD5FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD5BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD5BDLPUBA)
Input Stream Descriptor x Control (ISD6CTL_B0)
Input Stream Descriptor x Control (ISD6CTL_B2)
Input Stream Descriptor x Status (ISD6STS)
Input Stream Descriptor x Link Position in Buffer (ISD6LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD6CBL)
Input Stream Descriptor x Last Valid Index (ISD6LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD6FIFOW)
Input Stream Descriptor x FIFO Size (ISD6FIFOS)
Input Stream Descriptor x Format (ISD6FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD6BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD6BDLPUBA)
Input Stream Descriptor x Control (ISD7CTL_B0)
Input Stream Descriptor x Control (ISD7CTL_B2)
Input Stream Descriptor x Status (ISD7STS)
Input Stream Descriptor x Link Position in Buffer (ISD7LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD7CBL)
Input Stream Descriptor x Last Valid Index (ISD7LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD7FIFOW)
Input Stream Descriptor x FIFO Size (ISD7FIFOS)
Input Stream Descriptor x Format (ISD7FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD7BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD7BDLPUBA)
Input Stream Descriptor x Control (ISD8CTL_B0)
Input Stream Descriptor x Control (ISD8CTL_B2)
Input Stream Descriptor x Status (ISD8STS)
Input Stream Descriptor x Link Position in Buffer (ISD8LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD8CBL)
Input Stream Descriptor x Last Valid Index (ISD8LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD8FIFOW)
Input Stream Descriptor x FIFO Size (ISD8FIFOS)
Input Stream Descriptor x Format (ISD8FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD8BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD8BDLPUBA)
Input Stream Descriptor x Control (ISD9CTL_B0)
Input Stream Descriptor x Control (ISD9CTL_B2)
Input Stream Descriptor x Status (ISD9STS)
Input Stream Descriptor x Link Position in Buffer (ISD9LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD9CBL)
Input Stream Descriptor x Last Valid Index (ISD9LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD9FIFOW)
Input Stream Descriptor x FIFO Size (ISD9FIFOS)
Input Stream Descriptor x Format (ISD9FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD9BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD9BDLPUBA)
Output Stream Descriptor x Control (OSD0CTL_B0)
Output Stream Descriptor x Control (OSD0CTL_B2)
Output Stream Descriptor x Status (OSD0STS)
Output Stream Descriptor x Link Position in Buffer (OSD0LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD0CBL)
Output Stream Descriptor x Last Valid Index (OSD0LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD0FIFOW)
Output Stream Descriptor x FIFO Size (OSD0FIFOS)
Output Stream Descriptor x Format (OSD0FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD0BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD0BDLPUBA)
Output Stream Descriptor x Control (OSD1CTL_B0)
Output Stream Descriptor x Control (OSD1CTL_B2)
Output Stream Descriptor x Status (OSD1STS)
Output Stream Descriptor x Link Position in Buffer (OSD1LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD1CBL)
Output Stream Descriptor x Last Valid Index (OSD1LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD1FIFOW)
Output Stream Descriptor x FIFO Size (OSD1FIFOS)
Output Stream Descriptor x Format (OSD1FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD1BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD1BDLPUBA)
Output Stream Descriptor x Control (OSD2CTL_B0)
Output Stream Descriptor x Control (OSD2CTL_B2)
Output Stream Descriptor x Status (OSD2STS)
Output Stream Descriptor x Link Position in Buffer (OSD2LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD2CBL)
Output Stream Descriptor x Last Valid Index (OSD2LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD2FIFOW)
Output Stream Descriptor x FIFO Size (OSD2FIFOS)
Output Stream Descriptor x Format (OSD2FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD2BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD2BDLPUBA)
Output Stream Descriptor x Control (OSD3CTL_B0)
Output Stream Descriptor x Control (OSD3CTL_B2)
Output Stream Descriptor x Status (OSD3STS)
Output Stream Descriptor x Link Position in Buffer (OSD3LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD3CBL)
Output Stream Descriptor x Last Valid Index (OSD3LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD3FIFOW)
Output Stream Descriptor x FIFO Size (OSD3FIFOS)
Output Stream Descriptor x Format (OSD3FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD3BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD3BDLPUBA)
Output Stream Descriptor x Control (OSD4CTL_B0)
Output Stream Descriptor x Control (OSD4CTL_B2)
Output Stream Descriptor x Status (OSD4STS)
Output Stream Descriptor x Link Position in Buffer (OSD4LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD4CBL)
Output Stream Descriptor x Last Valid Index (OSD4LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD4FIFOW)
Output Stream Descriptor x FIFO Size (OSD4FIFOS)
Output Stream Descriptor x Format (OSD4FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD4BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD4BDLPUBA)
Output Stream Descriptor x Control (OSD5CTL_B0)
Output Stream Descriptor x Control (OSD5CTL_B2)
Output Stream Descriptor x Status (OSD5STS)
Output Stream Descriptor x Link Position in Buffer (OSD5LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD5CBL)
Output Stream Descriptor x Last Valid Index (OSD5LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD5FIFOW)
Output Stream Descriptor x FIFO Size (OSD5FIFOS)
Output Stream Descriptor x Format (OSD5FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD5BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD5BDLPUBA)
Output Stream Descriptor x Control (OSD6CTL_B0)
Output Stream Descriptor x Control (OSD6CTL_B2)
Output Stream Descriptor x Status (OSD6STS)
Output Stream Descriptor x Link Position in Buffer (OSD6LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD6CBL)
Output Stream Descriptor x Last Valid Index (OSD6LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD6FIFOW)
Output Stream Descriptor x FIFO Size (OSD6FIFOS)
Output Stream Descriptor x Format (OSD6FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD6BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD6BDLPUBA)
Output Stream Descriptor x Control (OSD7CTL_B0)
Output Stream Descriptor x Control (OSD7CTL_B2)
Output Stream Descriptor x Status (OSD7STS)
Output Stream Descriptor x Link Position in Buffer (OSD7LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD7CBL)
Output Stream Descriptor x Last Valid Index (OSD7LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD7FIFOW)
Output Stream Descriptor x FIFO Size (OSD7FIFOS)
Output Stream Descriptor x Format (OSD7FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD7BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD7BDLPUBA)
Output Stream Descriptor x Control (OSD8CTL_B0)
Output Stream Descriptor x Control (OSD8CTL_B2)
Output Stream Descriptor x Status (OSD8STS)
Output Stream Descriptor x Link Position in Buffer (OSD8LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD8CBL)
Output Stream Descriptor x Last Valid Index (OSD8LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD8FIFOW)
Output Stream Descriptor x FIFO Size (OSD8FIFOS)
Output Stream Descriptor x Format (OSD8FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD8BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD8BDLPUBA)
DMA Resume Capability Header (DRSMCH)
DMA Resume Control (DRSMCTL)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD0DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD1DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD2DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD3DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD4DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD5DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD6DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD7DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD8DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD9DPIBR)
Output Stream Descriptor x DMA Position in Buffer Resume (OSD0DPIBR)
Output Stream Descriptor x DMA Position in Buffer Resume (OSD1DPIBR)
Output Stream Descriptor x DMA Position in Buffer Resume (OSD2DPIBR)
Output Stream Descriptor x DMA Position in Buffer Resume (OSD3DPIBR)
Output Stream Descriptor x DMA Position in Buffer Resume (OSD4DPIBR)
Output Stream Descriptor x DMA Position in Buffer Resume (OSD5DPIBR)
Output Stream Descriptor x DMA Position in Buffer Resume (OSD6DPIBR)
Output Stream Descriptor x DMA Position in Buffer Resume (OSD7DPIBR)
Output Stream Descriptor x DMA Position in Buffer Resume (OSD8DPIBR)
Software Position Based FIFO Capability Header (SPBFCH)
Software Position Based FIFO Control (SPBFCTL)
Input Stream Descriptor x Software Position in Buffer (ISD0SPIB)
Input Stream Descriptor x Max FIFO Size (ISD0MAXFIFOS)
Input Stream Descriptor x Software Position in Buffer (ISD1SPIB)
Input Stream Descriptor x Max FIFO Size (ISD1MAXFIFOS)
Input Stream Descriptor x Software Position in Buffer (ISD2SPIB)
Input Stream Descriptor x Max FIFO Size (ISD2MAXFIFOS)
Input Stream Descriptor x Software Position in Buffer (ISD3SPIB)
Input Stream Descriptor x Max FIFO Size (ISD3MAXFIFOS)
Input Stream Descriptor x Software Position in Buffer (ISD4SPIB)
Input Stream Descriptor x Max FIFO Size (ISD4MAXFIFOS)
Input Stream Descriptor x Software Position in Buffer (ISD5SPIB)
Input Stream Descriptor x Max FIFO Size (ISD5MAXFIFOS)
Input Stream Descriptor x Software Position in Buffer (ISD6SPIB)
Input Stream Descriptor x Max FIFO Size (ISD6MAXFIFOS)
Input Stream Descriptor x Software Position in Buffer (ISD7SPIB)
Input Stream Descriptor x Max FIFO Size (ISD7MAXFIFOS)
Input Stream Descriptor x Software Position in Buffer (ISD8SPIB)
Input Stream Descriptor x Max FIFO Size (ISD8MAXFIFOS)
Input Stream Descriptor x Software Position in Buffer (ISD9SPIB)
Input Stream Descriptor x Max FIFO Size (ISD9MAXFIFOS)
Output Stream Descriptor x Software Position in Buffer (OSD0SPIB)
Output Stream Descriptor x Max FIFO Size (OSD0MAXFIFOS)
Output Stream Descriptor x Software Position in Buffer (OSD1SPIB)
Output Stream Descriptor x Max FIFO Size (OSD1MAXFIFOS)
Output Stream Descriptor x Software Position in Buffer (OSD2SPIB)
Output Stream Descriptor x Max FIFO Size (OSD2MAXFIFOS)
Output Stream Descriptor x Software Position in Buffer (OSD3SPIB)
Output Stream Descriptor x Max FIFO Size (OSD3MAXFIFOS)
Output Stream Descriptor x Software Position in Buffer (OSD4SPIB)
Output Stream Descriptor x Max FIFO Size (OSD4MAXFIFOS)
Output Stream Descriptor x Software Position in Buffer (OSD5SPIB)
Output Stream Descriptor x Max FIFO Size (OSD5MAXFIFOS)
Output Stream Descriptor x Software Position in Buffer (OSD6SPIB)
Output Stream Descriptor x Max FIFO Size (OSD6MAXFIFOS)
Output Stream Descriptor x Software Position in Buffer (OSD7SPIB)
Output Stream Descriptor x Max FIFO Size (OSD7MAXFIFOS)
Output Stream Descriptor x Software Position in Buffer (OSD8SPIB)
Output Stream Descriptor x Max FIFO Size (OSD8MAXFIFOS)
Processing Pipe Capability Header (PPCH)
Processing Pipe Control (PPCTL)
Processing Pipe Status (PPSTS)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC0LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC0LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC0LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC0LDPU)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC1LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC1LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC1LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC1LDPU)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC2LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC2LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC2LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC2LDPU)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC3LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC3LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC3LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC3LDPU)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC4LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC4LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC4LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC4LDPU)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC5LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC5LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC5LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC5LDPU)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC6LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC6LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC6LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC6LDPU)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC7LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC7LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC7LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC7LDPU)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC8LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC8LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC8LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC8LDPU)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC9LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC9LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC9LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC9LDPU)
Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC0LLPL)
Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC0LLPU)
Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC0LDPL)
Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC0LDPU)
Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC1LLPL)
Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC1LLPU)
Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC1LDPL)
Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC1LDPU)
Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC2LLPL)
Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC2LLPU)
Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC2LDPL)
Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC2LDPU)
Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC3LLPL)
Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC3LLPU)
Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC3LDPL)
Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC3LDPU)
Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC4LLPL)
Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC4LLPU)
Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC4LDPL)
Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC4LDPU)
Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC5LLPL)
Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC5LLPU)
Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC5LDPL)
Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC5LDPU)
Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC6LLPL)
Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC6LLPU)
Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC6LDPL)
Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC6LDPU)
Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC7LLPL)
Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC7LLPU)
Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC7LDPL)
Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC7LDPU)
Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC8LLPL)
Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC8LLPU)
Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC8LDPL)
Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC8LDPU)
Input Processing Pipe Link Connection x Control (IPPLC0CTL)
Input Processing Pipe Link Connection x Format (IPPLC0FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC0LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC0LLPU)
Input Processing Pipe Link Connection x Control (IPPLC1CTL)
Input Processing Pipe Link Connection x Format (IPPLC1FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC1LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC1LLPU)
Input Processing Pipe Link Connection x Control (IPPLC2CTL)
Input Processing Pipe Link Connection x Format (IPPLC2FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC2LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC2LLPU)
Input Processing Pipe Link Connection x Control (IPPLC3CTL)
Input Processing Pipe Link Connection x Format (IPPLC3FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC3LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC3LLPU)
Input Processing Pipe Link Connection x Control (IPPLC4CTL)
Input Processing Pipe Link Connection x Format (IPPLC4FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC4LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC4LLPU)
Input Processing Pipe Link Connection x Control (IPPLC5CTL)
Input Processing Pipe Link Connection x Format (IPPLC5FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC5LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC5LLPU)
Input Processing Pipe Link Connection x Control (IPPLC6CTL)
Input Processing Pipe Link Connection x Format (IPPLC6FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC6LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC6LLPU)
Input Processing Pipe Link Connection x Control (IPPLC7CTL)
Input Processing Pipe Link Connection x Format (IPPLC7FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC7LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC7LLPU)
Input Processing Pipe Link Connection x Control (IPPLC8CTL)
Input Processing Pipe Link Connection x Format (IPPLC8FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC8LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC8LLPU)
Input Processing Pipe Link Connection x Control (IPPLC9CTL)
Input Processing Pipe Link Connection x Format (IPPLC9FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC9LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC9LLPU)
Output Processing Pipe Link Connection x Control (OPPLC0CTL)
Output Processing Pipe Link Connection x Format (OPPLC0FMT)
Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC0LLPL)
Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC0LLPU)
Output Processing Pipe Link Connection x Control (OPPLC1CTL)
Output Processing Pipe Link Connection x Format (OPPLC1FMT)
Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC1LLPL)
Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC1LLPU)
Output Processing Pipe Link Connection x Control (OPPLC2CTL)
Output Processing Pipe Link Connection x Format (OPPLC2FMT)
Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC2LLPL)
Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC2LLPU)
Output Processing Pipe Link Connection x Control (OPPLC3CTL)
Output Processing Pipe Link Connection x Format (OPPLC3FMT)
Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC3LLPL)
Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC3LLPU)
Output Processing Pipe Link Connection x Control (OPPLC4CTL)
Output Processing Pipe Link Connection x Format (OPPLC4FMT)
Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC4LLPL)
Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC4LLPU)
Output Processing Pipe Link Connection x Control (OPPLC5CTL)
Output Processing Pipe Link Connection x Format (OPPLC5FMT)
Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC5LLPL)
Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC5LLPU)
Output Processing Pipe Link Connection x Control (OPPLC6CTL)
Output Processing Pipe Link Connection x Format (OPPLC6FMT)
Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC6LLPL)
Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC6LLPU)
Output Processing Pipe Link Connection x Control (OPPLC7CTL)
Output Processing Pipe Link Connection x Format (OPPLC7FMT)
Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC7LLPL)
Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC7LLPU)
Output Processing Pipe Link Connection x Control (OPPLC8CTL)
Output Processing Pipe Link Connection x Format (OPPLC8FMT)
Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC8LLPL)
Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC8LLPU)
Multiple Links Capability Header (MLCH)
Multiple Links Capability Declaration (MLCD)
Input Stream Descriptor x DMA Position in Buffer (ISD0DPIB)
Input Stream Descriptor x DMA Position in Buffer (ISD1DPIB)
Input Stream Descriptor x DMA Position in Buffer (ISD2DPIB)
Input Stream Descriptor x DMA Position in Buffer (ISD3DPIB)
Input Stream Descriptor x DMA Position in Buffer (ISD4DPIB)
Input Stream Descriptor x DMA Position in Buffer (ISD5DPIB)
Function Configuration (FNCFG)
Wall Clock Counter (WALCLKA)
Input Stream Descriptor x Link Position in Buffer (ISD0LPIBA)
Input Stream Descriptor x Link Position in Buffer (ISD1LPIBA)
Input Stream Descriptor x Link Position in Buffer (ISD2LPIBA)
Input Stream Descriptor x Link Position in Buffer (ISD3LPIBA)
Input Stream Descriptor x Link Position in Buffer (ISD4LPIBA)
Input Stream Descriptor x Link Position in Buffer (ISD5LPIBA)
Input Stream Descriptor x Link Position in Buffer (ISD6LPIBA)
Input Stream Descriptor x Link Position in Buffer (ISD7LPIBA)
Input Stream Descriptor x Link Position in Buffer (ISD8LPIBA)
Input Stream Descriptor x Link Position in Buffer (ISD9LPIBA)
Output Stream Descriptor x Link Position in Buffer (OSD0LPIBA)
Output Stream Descriptor x Link Position in Buffer (OSD1LPIBA)
Output Stream Descriptor x Link Position in Buffer (OSD2LPIBA)
Output Stream Descriptor x Link Position in Buffer (OSD3LPIBA)
Output Stream Descriptor x Link Position in Buffer (OSD4LPIBA)
Output Stream Descriptor x Link Position in Buffer (OSD5LPIBA)
Output Stream Descriptor x Link Position in Buffer (OSD6LPIBA)
Output Stream Descriptor x Link Position in Buffer (OSD7LPIBA)
Output Stream Descriptor x Link Position in Buffer (OSD8LPIBA)
ACE PCI Configuration
Vendor Identification (VID)
Device Identification (DID)
Device Command (CMD)
Device Status (STS)
Revision Identification (RID)
Programming Interface (PI)
Sub Class Code (SCC)
Base Class Code (BCC)
Cache Line Size (CLS)
Latency Timer (LT)
Header Type (HTYPE)
Intel HD Audio Lower Base Address (HDALBA)
Intel HD Audio Upper Base Address (HDAUBA)
Shadowed PCI Configuration Lower Base Address (SPCLBA)
Shadowed PCI Configuration Upper Base Address (SPCUBA)
DSP Subsystem Lower Base Address (DSPLBA)
DSP Subsystem Upper Base Address (DSPUBA)
Subsystem Vendor Identifier (SVID)
Subsystem Identifier (SID)
Capabilities Pointer (CAPPTR)
Interrupt Line (INTLN)
Interrupt Pin (INTPN)
Power Management Identifiers (PID)
Power Management Capabilities (PC)
Power Management Control & Status (PCS)
MSI Identifiers (MID)
MSI Message Control (MMC)
MSI Message Lower Address (MMLA)
MSI Message Upper Address (MMUA)
MSI Message Data (MMD)
PCI Express Identifiers (PXID)
PCI Express Capabilities (PXC)
Device Capabilities (DEVCAP)
Device Control (DEVC)
Device Status (DEVS)
Vendor Specific Capability Identifiers (VSCID)
Vendor Specific Extended Capability Identifiers (VSECID)
Device Idle Pointer (DEVIDLEPTR)
Device Idle Power On Latency (DEVIDLEPOL)
Power Control Enable (PCE)
Advanced Programmable Interrupt (APIC) Index
Identification Register (IDR)
Version Register (VS)
Redirection Table Entry 0 (RTE0)
Redirection Table Entry 1 (RTE1)
Redirection Table Entry 2 (RTE2)
Redirection Table Entry 3 (RTE3)
Redirection Table Entry 4 (RTE4)
Redirection Table Entry 5 (RTE5)
Redirection Table Entry 6 (RTE6)
Redirection Table Entry 7 (RTE7)
Redirection Table Entry 8 (RTE8)
Redirection Table Entry 9 (RTE9)
Redirection Table Entry 10 (RTE10)
Redirection Table Entry 11 (RTE11)
Redirection Table Entry 12 (RTE12)
Redirection Table Entry 13 (RTE13)
Redirection Table Entry 14 (RTE14)
Redirection Table Entry 15 (RTE15)
Redirection Table Entry 16 (RTE16)
Redirection Table Entry 17 (RTE17)
Redirection Table Entry 18 (RTE18)
Redirection Table Entry 19 (RTE19)
Redirection Table Entry 20 (RTE20)
Redirection Table Entry 21 (RTE21)
Redirection Table Entry 22 (RTE22)
Redirection Table Entry 23 (RTE23)
Redirection Table Entry 24 (RTE24)
Redirection Table Entry 25 (RTE25)
Redirection Table Entry 26 (RTE26)
Redirection Table Entry 27 (RTE27)
Redirection Table Entry 28 (RTE28)
Redirection Table Entry 29 (RTE29)
Redirection Table Entry 30 (RTE30)
Redirection Table Entry 31 (RTE31)
Redirection Table Entry 32 (RTE32)
Redirection Table Entry 33 (RTE33)
Redirection Table Entry 34 (RTE34)
Redirection Table Entry 35 (RTE35)
Redirection Table Entry 36 (RTE36)
Redirection Table Entry 37 (RTE37)
Redirection Table Entry 38 (RTE38)
Redirection Table Entry 39 (RTE39)
Redirection Table Entry 40 (RTE40)
Redirection Table Entry 41 (RTE41)
Redirection Table Entry 42 (RTE42)
Redirection Table Entry 43 (RTE43)
Redirection Table Entry 44 (RTE44)
Redirection Table Entry 45 (RTE45)
Redirection Table Entry 46 (RTE46)
Redirection Table Entry 47 (RTE47)
Redirection Table Entry 48 (RTE48)
Redirection Table Entry 49 (RTE49)
Redirection Table Entry 50 (RTE50)
Redirection Table Entry 51 (RTE51)
Redirection Table Entry 52 (RTE52)
Redirection Table Entry 53 (RTE53)
Redirection Table Entry 54 (RTE54)
Redirection Table Entry 55 (RTE55)
Redirection Table Entry 56 (RTE56)
Redirection Table Entry 57 (RTE57)
Redirection Table Entry 58 (RTE58)
Redirection Table Entry 59 (RTE59)
Redirection Table Entry 60 (RTE60)
Redirection Table Entry 61 (RTE61)
Redirection Table Entry 62 (RTE62)
Redirection Table Entry 63 (RTE63)
Redirection Table Entry 64 (RTE64)
Redirection Table Entry 65 (RTE65)
Redirection Table Entry 66 (RTE66)
Redirection Table Entry 67 (RTE67)
Redirection Table Entry 68 (RTE68)
Redirection Table Entry 69 (RTE69)
Redirection Table Entry 70 (RTE70)
Redirection Table Entry 71 (RTE71)
Redirection Table Entry 72 (RTE72)
Redirection Table Entry 73 (RTE73)
Redirection Table Entry 74 (RTE74)
Redirection Table Entry 75 (RTE75)
Redirection Table Entry 76 (RTE76)
Redirection Table Entry 77 (RTE77)
Redirection Table Entry 78 (RTE78)
Redirection Table Entry 79 (RTE79)
Redirection Table Entry 80 (RTE80)
Redirection Table Entry 81 (RTE81)
Redirection Table Entry 82 (RTE82)
Redirection Table Entry 83 (RTE83)
Redirection Table Entry 84 (RTE84)
Redirection Table Entry 85 (RTE85)
Redirection Table Entry 86 (RTE86)
Redirection Table Entry 87 (RTE87)
Redirection Table Entry 88 (RTE88)
Redirection Table Entry 89 (RTE89)
Redirection Table Entry 90 (RTE90)
Redirection Table Entry 91 (RTE91)
Redirection Table Entry 92 (RTE92)
Redirection Table Entry 93 (RTE93)
Redirection Table Entry 94 (RTE94)
Redirection Table Entry 95 (RTE95)
Redirection Table Entry 96 (RTE96)
Redirection Table Entry 97 (RTE97)
Redirection Table Entry 98 (RTE98)
Redirection Table Entry 99 (RTE99)
Redirection Table Entry 100 (RTE100)
Redirection Table Entry 101 (RTE101)
Redirection Table Entry 102 (RTE102)
Redirection Table Entry 103 (RTE103)
Redirection Table Entry 104 (RTE104)
Redirection Table Entry 105 (RTE105)
Redirection Table Entry 106 (RTE106)
Redirection Table Entry 107 (RTE107)
Redirection Table Entry 108 (RTE108)
Redirection Table Entry 109 (RTE109)
Redirection Table Entry 110 (RTE110)
Redirection Table Entry 111 (RTE111)
Redirection Table Entry 112 (RTE112)
Redirection Table Entry 113 (RTE113)
Redirection Table Entry 114 (RTE114)
Redirection Table Entry 115 (RTE115)
Redirection Table Entry 116 (RTE116)
Redirection Table Entry 117 (RTE117)
Redirection Table Entry 118 (RTE118)
Redirection Table Entry 119 (RTE119)
CNVi WiFi* PCI Configuration
Vendor Device Identification (CNVI_WIFI_VEN_DEV_ID)
PCI Command and Status (CNVI_WIFI_PCI_COM_STAT)
Revision Identifier and Class Code (CNVI_WIFI_PCI_CLASS_CODE)
BUS COM (CNVI_WIFI_PCI_BUS_COM)
BAR 0 (CNVI_WIFI_BAR0)
BAR 1 (CNVI_WIFI_BAR1)
CNVI WIFI SUBSYS Identification (CNVI_WIFI_BAR2)
CNVI WIFI ROM (Read Only Memory) BAR (CNVI_WIFI_BAR3)
CNVI WIFI BAR [4] (CNVI_WIFI_BAR4)
CNVI WIFI BAR [5] (CNVI_WIFI_BAR5)
CNVI WIFI CIS PTR (CNVI_WIFI_CIS_PTR)
Sub System Identification (CNVI_WIFI_SUBSYS_ID)
ROM BAR (CNVI_WIFI_ROM_BAR)
Capability Pointer (CNVI_WIFI_CAP_PTR)
CNVI WIFI RES ADDRESS (CNVI_WIFI_RES_ADDRESS)
Interrupt (CNVI_WIFI_INTERRUPT)
Capability (CNVI_WIFI_GIO_CAP)
Device Capability (CNVI_WIFI_GIO_DEV_CAP)
Device Control (CNVI_WIFI_GIO_DEV)
CNVI WIFI GIO LNK Capability (CNVI_WIFI_GIO_LNK_CAP)
CNVI WIFI GIO LINK (CNVI_WIFI_GIO_LINK)
Device Capability 2 (CNVI_WIFI_GIO_DEV_CAP_2)
Device Control 2 (CNVI_WIFI_GIO_DEV_2)
CNVI WIFI GIO LINK [2] (CNVI_WIFI_GIO_LINK_2)
MSIX Capability HEAD (CNVI_WIFI_MSIX_CAP_HEAD)
MSIX TABLE OFFSET (CNVI_WIFI_MSIX_TABLE_OFFSET)
MSIX PBA OFFSET (CNVI_WIFI_MSIX_PBA_OFFSET)
Power Management Capabilities (CNVI_WIFI_PMC)
Power Management Status and Control (CNVI_WIFI_PMCSR)
MSI Message Control (CNVI_WIFI_MSI_MSG_CTRL)
MSI LOW Address (CNVI_WIFI_MSI_LOW_ADD)
MSI HIGH Address (CNVI_WIFI_MSI_HIGH_ADD)
MSI Data (CNVI_WIFI_MSI_DATA)
LTR Extended Capability (CNVI_WIFI_LTR_EXTND_CAP_HEAD)
LTR Maximum Snoop NoSnoop Latency (CNVI_WIFI_LTR_MAX_SNOOP_NOSNOOP_LAT)
Uncorrectable Error Severity (CNVI_WIFI_UNCORRECT_ERR_SEV)
Correctable Error Status (CNVI_WIFI_CORRECT_ERR_STAT)
Correctable Error Mask (CNVI_WIFI_CORRECT_ERR_MASK)
Advanced Error Capability (CNVI_WIFI_ADVANCED_ERR_CAP)
Header Log 1 (CNVI_WIFI_HEADER_LOG1)
Header Log 2 (CNVI_WIFI_HEADER_LOG2)
Header Log 3 (CNVI_WIFI_HEADER_LOG3)
Header Log 4 (CNVI_WIFI_HEADER_LOG4)
GIO Serial Capability (CNVI_WIFI_GIO_SERIAL_CAP)
GIO Serial Number Low (CNVI_WIFI_GIO_SERIAL_LOW)
GIO Serial Number Up (CNVI_WIFI_GIO_SERIAL_UP)
L1 Substates Extended Capability Header (CNVI_WIFI_L1PM_SUB_EXTND_CAP_HEAD)
L1 Substates Capability (CNVI_WIFI_L1PM_SUB_CAP)
L1 Substates Control (CNVI_WIFI_L1PM_SUB_CNTRL)
L1 Substates Control 2 (CNVI_WIFI_L1PM_SUB_CNTRL2)
Vendor Specific Capability (CNVI_WIFI_VEN_SPEC_CAP)
Vendor Specific Extended Capability (CNVI_WIFI_VEN_SPEC_EXTND_CAP)
SW LTP Pointer (CNVI_WIFI_LTP_PTR)
Device Idle Pointer (CNVI_WIFI_DEV_IDLE_PTR)
Device Idle Power (CNVI_WIFI_DEV_IDLE_PWR)
eSPI PCI Configuration (D31:F0)
Device and Vendor Identifiers (ESPI_DID_VID)
Device Status and Command (ESPI_STS_CMD)
Class Code and Revision ID (ESPI_CC_RID)
Peripheral Channel Header Type and Primary Latency (ESPI_PCHT_PCPLT)
Sub System Identifiers (ESPI_SS)
Capability List Pointer (ESPI_CAPP)
I/O Decode Ranges and I/O Enables (ESPI_IOD_IOE)
eSPI Generic IO Range 1 (ESPI_LGIR1)
eSPI Generic IO Range 2 (ESPI_LGIR2)
eSPI Generic IO Range 3 (ESPI_LGIR3)
eSPI Generic IO Range 4 (ESPI_LGIR4)
USB Legacy Keyboard/Mouse Control (ESPI_ULKMC)
eSPI Generic Memory Range (ESPI_LGMR)
eSPI CS1 IO Routing Enables (ESPI_CS1IORE)
eSPI CS1 Generic IO Range 1 (ESPI_CS1GIR1)
eSPI CS1 Generic Memory Range 1 (ESPI_CS1GMR1)
BIOS Decode Enable (ESPI_BDE)
BIOS Control (ESPI_BC)
eSPI IO Routing Enables for ESPI CS2 (ESPI_IORE_EXT[2])
eSPI Generic IO Range 1 for ESPI CS2 (ESPI_GIR1_EXT[2])
eSPI Generic Memory Range 1 for ESPI CS2 (ESPI_GMR1_EXT[2])
eSPI IO Routing Enables for ESPI CS3 (ESPI_IORE_EXT[3])
eSPI Generic IO Range 1 for ESPI CS3 (ESPI_GIR1_EXT[3])
eSPI Generic Memory Range 1 for ESPI CS3 (ESPI_GMR1_EXT[3])
eSPI PCR
eSPI Device Configuration Register And Link Control (SLV_CFG_REG_CTL)
eSPI Device Configuration Register Data (SLV_CFG_REG_DATA)
Peripheral Channel Error for Device 0 (PCERR_SLV0)
Peripheral Channel Error for Device 1 (PCERR_SLV1)
Virtual Wire Channel Error for Device 0 (VWERR_SLV0)
Virtual Wire Channel Error for Device 1 (VWERR_SLV1)
Flash Access Channel Error for Device 0 (FCERR_SLV0)
Link Error for Device 0 (LNKERR_SLV0)
Link Error for Device 1 (LNKERR_SLV1)
Peripheral Channel Error for Device 2 (PCERR_SLV2)
Virtual Wire Channel Error for Device 2 (VWERR_SLV2)
Link Error for Device 2 (LNKERR_SLV2)
Peripheral Channel Error for Device 3 (PCERR_SLV3)
Virtual Wire Channel Error for Device 3 (VWERR_SLV3)
Link Error for Device 3 (LNKERR_SLV3)
GPIO Community 0
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_GPP_V_0)
Pad Ownership (PAD_OWN_GPP_V_1)
Pad Ownership (PAD_OWN_GPP_V_2)
Pad Ownership (PAD_OWN_GPP_C_0)
Pad Ownership (PAD_OWN_GPP_C_1)
Pad Ownership (PAD_OWN_GPP_C_2)
Pad Configuration Lock (PADCFGLOCK_GPP_V_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_V_0)
Pad Configuration Lock (PADCFGLOCK_GPP_C_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_C_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_V_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_C_0)
GPI Interrupt Status (GPI_IS_GPP_V_0)
GPI Interrupt Status (GPI_IS_GPP_C_0)
GPI Interrupt Enable (GPI_IE_GPP_V_0)
GPI Interrupt Enable (GPI_IE_GPP_C_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_V_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_V_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_0)
GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET)
GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET)
GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_0)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_4)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_4)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_6)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_6)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_7)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_8)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_8)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_9)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_9)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_10)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_10)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_11)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_11)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_12)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_12)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_13)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_13)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_14)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_14)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_15)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_15)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_16)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_16)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_17)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_17)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_0)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_4)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_4)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_6)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_6)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_7)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_8)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_8)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_9)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_9)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_10)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_10)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_11)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_11)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_12)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_12)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_13)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_13)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_14)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_14)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_15)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_15)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_16)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_16)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_17)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_17)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_18)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_18)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_19)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_19)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_20)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_20)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_21)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_21)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_22)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_22)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_23)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_23)
GPIO Community 1
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_GPP_F_0)
Pad Ownership (PAD_OWN_GPP_F_1)
Pad Ownership (PAD_OWN_GPP_F_2)
Pad Ownership (PAD_OWN_GPP_E_0)
Pad Ownership (PAD_OWN_GPP_E_1)
Pad Ownership (PAD_OWN_GPP_E_2)
Pad Configuration Lock (PADCFGLOCK_GPP_F_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_F_0)
Pad Configuration Lock (PADCFGLOCK_GPP_E_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_E_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_F_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_E_0)
GPI Interrupt Status (GPI_IS_GPP_F_0)
GPI Interrupt Status (GPI_IS_GPP_E_0)
GPI Interrupt Enable (GPI_IE_GPP_F_0)
GPI Interrupt Enable (GPI_IE_GPP_E_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_E_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_E_0)
SMI Status (GPI_SMI_STS_GPP_E_0)
SMI Enable (GPI_SMI_EN_GPP_E_0)
NMI Status (GPI_NMI_STS_GPP_E_0)
NMI Enable (GPI_NMI_EN_GPP_E_0)
GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET)
GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET)
GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET)
GPIO Hardware Information NMI Int Offset (NMI_INT_OFFSET)
GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_0)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_4)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_4)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_6)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_6)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_7)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_8)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_8)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_9)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_9)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_10)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_10)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_11)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_11)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_12)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_12)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_13)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_13)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_14)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_14)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_15)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_15)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_16)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_16)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_17)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_17)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_18)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_18)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_19)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_19)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_20)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_20)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_21)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_21)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_22)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_22)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_23)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_23)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_0)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_4)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_4)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_6)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_6)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_7)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_8)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_8)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_9)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_9)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_10)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_10)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_11)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_11)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_12)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_12)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_13)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_13)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_14)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_14)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_15)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_15)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_16)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_16)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_17)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_17)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_18)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_18)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_19)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_19)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_20)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_20)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_21)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_21)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_22)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_22)
GPIO Community 3
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_GPPASPI0_0)
Pad Ownership (PAD_OWN_GPPASPI0_1)
Pad Ownership (PAD_OWN_GPP_H_0)
Pad Ownership (PAD_OWN_GPP_H_1)
Pad Ownership (PAD_OWN_GPP_H_2)
Pad Configuration Lock (PADCFGLOCK_GPPASPI0_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPPASPI0_0)
Pad Configuration Lock (PADCFGLOCK_GPP_H_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_H_0)
Host Software Pad Ownership (HOSTSW_OWN_GPPASPI0_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_H_0)
GPI Interrupt Status (GPI_IS_GPPASPI0_0)
GPI Interrupt Status (GPI_IS_GPP_H_0)
GPI Interrupt Enable (GPI_IE_GPPASPI0_0)
GPI Interrupt Enable (GPI_IE_GPP_H_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPPASPI0_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_H_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPPASPI0_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_H_0)
GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET)
GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET)
GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_0)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_4)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_4)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_6)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_6)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_7)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_8)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_8)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_9)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_9)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_10)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_10)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_11)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_11)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_12)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_12)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_13)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_13)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_14)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_14)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_15)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_15)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_0)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_4)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_4)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_6)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_6)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_7)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_8)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_8)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_9)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_9)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_10)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_10)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_11)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_11)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_12)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_12)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_13)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_13)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_14)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_14)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_15)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_15)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_16)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_16)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_17)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_17)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_18)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_18)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_19)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_19)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_20)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_20)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_21)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_21)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_22)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_22)
GPIO Community 4
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_GPP_S_0)
Pad Configuration Lock (PADCFGLOCK_GPP_S_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_S_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_S_0)
GPI Interrupt Status (GPI_IS_GPP_S_0)
GPI Interrupt Enable (GPI_IE_GPP_S_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_S_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_S_0)
GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET)
GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET)
GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_0)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_4)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_4)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_6)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_6)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_7)
GPIO Community 5
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_GPP_B_0)
Pad Ownership (PAD_OWN_GPP_B_1)
Pad Ownership (PAD_OWN_GPP_B_2)
Pad Ownership (PAD_OWN_GPP_D_0)
Pad Ownership (PAD_OWN_GPP_D_1)
Pad Ownership (PAD_OWN_GPP_D_2)
Pad Configuration Lock (PADCFGLOCK_GPP_B_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_B_0)
Pad Configuration Lock (PADCFGLOCK_GPP_D_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_D_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_B_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_D_0)
GPI Interrupt Status (GPI_IS_GPP_B_0)
GPI Interrupt Status (GPI_IS_GPP_D_0)
GPI Interrupt Enable (GPI_IE_GPP_B_0)
GPI Interrupt Enable (GPI_IE_GPP_D_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_D_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_B_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_D_0)
SMI Status (GPI_SMI_STS_GPP_B_0)
SMI Status (GPI_SMI_STS_GPP_D_0)
SMI Enable (GPI_SMI_EN_GPP_B_0)
SMI Enable (GPI_SMI_EN_GPP_D_0)
NMI Status (GPI_NMI_STS_GPP_B_0)
NMI Status (GPI_NMI_STS_GPP_D_0)
NMI Enable (GPI_NMI_EN_GPP_B_0)
NMI Enable (GPI_NMI_EN_GPP_D_0)
GPIO Hardware Information GPI Int Offset (GPI_INT_OFFSET)
GPIO Hardware Information GPI GPE Int Offset (GPI_GPE_INT_OFFSET)
GPIO Hardware Information SMI Int Offset (SMI_INT_OFFSET)
GPIO Hardware Information NMI Int Offset (NMI_INT_OFFSET)
GPIO Hardware Information PAD and HOSTSW Own Offset (PAD_AND_HOSTSW_OWN_OFFSET)
PWM Control (PWMC)
GPIO Serial Blink Enable (GP_SER_BLINK)
GPIO Serial Blink Command/Status (GP_SER_CMDSTS)
GPIO Serial Blink Data (GP_SER_DATA)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_0)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_4)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_4)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_6)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_6)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_7)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_8)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_8)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_9)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_9)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_10)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_10)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_11)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_11)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_12)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_12)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_13)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_13)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_14)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_14)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_15)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_15)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_16)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_16)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_17)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_17)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_18)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_18)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_19)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_19)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_20)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_20)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_21)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_21)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_22)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_22)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_23)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_23)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_0)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_4)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_4)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_6)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_6)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_7)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_8)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_8)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_9)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_9)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_10)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_10)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_11)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_11)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_12)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_12)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_13)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_13)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_14)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_14)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_15)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_15)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_16)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_16)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_17)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_17)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_18)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_18)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_19)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_19)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_20)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_20)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_21)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_21)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_22)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_22)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_23)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_23)
GSPI Additional MMIO
REG CLOCKS (CLOCKS)
REG RESETS (RESETS)
REG ACTIVELTR_VALUE (ACTIVELTR_VALUE)
REG IDLELTR_VALUE (IDLELTR_VALUE)
REG TX_BIT_COUNT (TX_BIT_COUNT)
REG RX_BIT_COUNT (RX_BIT_COUNT)
REG SSP_REG (SSP_REG)
REG SPI_CS_CONTROL (SPI_CS_CONTROL)
REG SW_SCRATCH_0 (SW_SCRATCH_0)
REG SW_SCRATCH_1 (SW_SCRATCH_1)
REG SW_SCRATCH_2 (SW_SCRATCH_2)
REG SW_SCRATCH_3 (SW_SCRATCH_3)
REG CLOCK_GATE (CLOCK_GATE)
REG REMAP_ADDR_LO (REMAP_ADDR_LO)
REG REMAP_ADDR_HI (REMAP_ADDR_HI)
REG DEVIDLE_CONTROL (DEVIDLE_CONTROL)
REG DEL_RX_CLK (DEL_RX_CLK)
REG CAPABLITIES (CAPABLITIES)
GSPI DMA Controller
REG SAR_LO0 (SAR_LO0)
REG SAR_HI0 (SAR_HI0)
REG DAR_LO0 (DAR_LO0)
REG DAR_HI0 (DAR_HI0)
REG LLP_LO0 (LLP_LO0)
REG LLP_HI0 (LLP_HI0)
REG CTL_LO0 (CTL_LO0)
REG CTL_HI0 (CTL_HI0)
REG SSTAT0 (SSTAT0)
REG DSTAT0 (DSTAT0)
REG SSTATAR_LO0 (SSTATAR_LO0)
REG SSTATAR_HI0 (SSTATAR_HI0)
REG DSTATAR_LO0 (DSTATAR_LO0)
REG DSTATAR_HI0 (DSTATAR_HI0)
REG CFG_LO0 (CFG_LO0)
REG CFG_HI0 (CFG_HI0)
REG SGR0 (SGR0)
REG DSR0 (DSR0)
REG SAR_LO1 (SAR_LO1)
REG SAR_HI1 (SAR_HI1)
REG DAR_LO1 (DAR_LO1)
REG DAR_HI1 (DAR_HI1)
REG LLP_LO1 (LLP_LO1)
REG LLP_HI1 (LLP_HI1)
REG CTL_LO1 (CTL_LO1)
REG CTL_HI1 (CTL_HI1)
REG SSTAT1 (SSTAT1)
REG DSTAT1 (DSTAT1)
REG SSTATAR_LO1 (SSTATAR_LO1)
REG SSTATAR_HI1 (SSTATAR_HI1)
REG DSTATAR_LO1 (DSTATAR_LO1)
REG DSTATAR_HI1 (DSTATAR_HI1)
REG CFG_LO1 (CFG_LO1)
REG CFG_HI1 (CFG_HI1)
REG SGR1 (SGR1)
REG DSR1 (DSR1)
REG RawTfr (RawTfr)
REG RawBlock (RawBlock)
REG RawSrcTran (RawSrcTran)
REG RawDstTran (RawDstTran)
REG RawErr (RawErr)
REG StatusTfr (StatusTfr)
REG StatusBlock (StatusBlock)
REG StatusSrcTran (StatusSrcTran)
REG StatusDstTran (StatusDstTran)
REG StatusErr (StatusErr)
REG MaskTfr (MaskTfr)
REG MaskBlock (MaskBlock)
REG MaskSrcTran (MaskSrcTran)
REG MaskDstTran (MaskDstTran)
REG MaskErr (MaskErr)
REG ClearTfr (ClearTfr)
REG ClearBlock (ClearBlock)
REG ClearSrcTran (ClearSrcTran)
REG ClearDstTran (ClearDstTran)
REG ClearErr (ClearErr)
REG StatusInt (StatusInt)
REG DmaCfgReg (DmaCfgReg)
REG ChEnReg (ChEnReg)
REG Reserved0_CPL (Reserved0_CPL)
REG Reserved0_CPH (Reserved0_CPH)
REG Reserved1_CPL (Reserved1_CPL)
REG Reserved1_CPH (Reserved1_CPH)
REG Reserved0_FPL (Reserved0_FPL)
REG Reserved0_FPH (Reserved0_FPH)
REG Reserved1_FPL (Reserved1_FPL)
REG Reserved1_FPH (Reserved1_FPH)
REG SAI_ERR (SAI_ERR)
REG GLOBAL_CFG (GLOBAL_CFG)
GSPI PCI Configuration (D30:F2/3, D18:F6)
Device Id And Vendor Id Register (DEVVENDID)
Status And Command (STATUSCOMMAND)
Revision Id And Class Code (REVCLASSCODE)
Cache Line Latency Header And Bist (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Subsystem Vendor And Subsystem Id (SUBSYSTEMID)
Expansion Rom Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer Register (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Control And Status Register (PMECTRLSTATUS)
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)
High Precision Event Timer (HPET) MMIO
General Capabilities and ID Register (GEN_CAP_ID)
General Config Register (GEN_CFG)
General Interrupt Status Register (GEN_INT_STS)
Main Counter Value (MAIN_CNTR)
Timer 0 Config and Capabilities (TMR0_CNF_CAP)
Timer 0 Comparator Value (TMR0_CMP_VAL)
Timer 0 FSB Interrupt Rout Register (TMR0_FSB_INT_ROUT)
Timer 1 Config and Capabilities (TMR1_CNF_CAP)
Timer 1 Comparator Value (TMR1_CMP_VAL)
Timer 1 FSB Interrupt Rout Register (TMR1_FSB_INT_ROUT)
Timer 2 Config and Capabilities (TMR2_CNF_CAP)
Timer 2 Comparator Value (TMR2_CMP_VAL)
Timer 2 FSB Interrupt Rout Register (TMR2_FSB_INT_ROUT)
Timer 3 Config and Capabilities (TMR3_CNF_CAP)
Timer 3 Comparator Value (TMR3_CMP_VAL)
Timer 3 FSB Interrupt Rout Register (TMR3_FSB_INT_ROUT)
Timer 4 Config and Capabilities (TMR4_CNF_CAP)
Timer 4 Comparator Value (TMR4_CMP_VAL)
Timer 4 FSB Interrupt Rout Register (TMR4_FSB_INT_ROUT)
Timer 5 Config and Capabilities (TMR5_CNF_CAP)
Timer 5 Comparator Value (TMR5_CMP_VAL)
Timer 5 FSB Interrupt Rout Register (TMR5_FSB_INT_ROUT)
Timer 6 Config and Capabilities (TMR6_CNF_CAP)
Timer 6 Comparator Value (TMR6_CMP_VAL)
Timer 6 FSB Interrupt Rout Register (TMR6_FSB_INT_ROUT)
Timer 7 Config and Capabilities (TMR7_CNF_CAP)
Timer 7 Comparator Value (TMR7_CMP_VAL)
Timer 7 FSB Interrupt Rout Register (TMR7_FSB_INT_ROUT)
I2C Additional MMIO
(Reserved0)
Resets (RESETS)
General (GENERAL)
Active LTR Value (ACTIVELTR_VALUE)
Idle LTR Value (IDLELTR_VALUE)
TX ACK Counts (TX_ACK_COUNT)
RX ACK Counts (RX_BYTE_COUNT)
Interrupt Status for Tx Complete (TX_COMPLETE_INTR_STAT)
Tx Complete Interrupt Clear (TX_COMPLETE_INTR_CLR)
SW scratch register 0 (SW_SCRATCH_0)
SW scratch register 1 (SW_SCRATCH_1)
SW scratch register 2 (SW_SCRATCH_2)
SW scratch register 3 (SW_SCRATCH_3)
Clock Gate (CLOCK_GATE)
(Reserved1)
Remap Address Low (REMAP_ADDR_LO)
Remap Address High (REMAP_ADDR_HI)
(Reserved2)
Device Idle Control (DEVIDLE_CONTROL)
REG I2C_HVM_MISR_CRCOUT (I2C_HVM_MISR_CRCOUT)
Capabilities (CAPABLITIES)
I2C DMA Controller
REG SAR_LO0 (SAR_LO0)
REG SAR_HI0 (SAR_HI0)
REG DAR_LO0 (DAR_LO0)
REG DAR_HI0 (DAR_HI0)
REG LLP_LO0 (LLP_LO0)
REG LLP_HI0 (LLP_HI0)
REG CTL_LO0 (CTL_LO0)
REG CTL_HI0 (CTL_HI0)
REG SSTAT0 (SSTAT0)
REG DSTAT0 (DSTAT0)
REG SSTATAR_LO0 (SSTATAR_LO0)
REG SSTATAR_HI0 (SSTATAR_HI0)
REG DSTATAR_LO0 (DSTATAR_LO0)
REG DSTATAR_HI0 (DSTATAR_HI0)
REG CFG_LO0 (CFG_LO0)
REG CFG_HI0 (CFG_HI0)
REG SGR0 (SGR0)
REG DSR0 (DSR0)
REG SAR_LO1 (SAR_LO1)
REG SAR_HI1 (SAR_HI1)
REG DAR_LO1 (DAR_LO1)
REG DAR_HI1 (DAR_HI1)
REG LLP_LO1 (LLP_LO1)
REG LLP_HI1 (LLP_HI1)
REG CTL_LO1 (CTL_LO1)
REG CTL_HI1 (CTL_HI1)
REG SSTAT1 (SSTAT1)
REG DSTAT1 (DSTAT1)
REG SSTATAR_LO1 (SSTATAR_LO1)
REG SSTATAR_HI1 (SSTATAR_HI1)
REG DSTATAR_LO1 (DSTATAR_LO1)
REG DSTATAR_HI1 (DSTATAR_HI1)
REG CFG_LO1 (CFG_LO1)
REG CFG_HI1 (CFG_HI1)
REG SGR1 (SGR1)
REG DSR1 (DSR1)
REG RawTfr (RawTfr)
REG RawBlock (RawBlock)
REG RawSrcTran (RawSrcTran)
REG RawDstTran (RawDstTran)
REG RawErr (RawErr)
REG StatusTfr (StatusTfr)
REG StatusBlock (StatusBlock)
REG StatusSrcTran (StatusSrcTran)
REG StatusDstTran (StatusDstTran)
REG StatusErr (StatusErr)
REG MaskTfr (MaskTfr)
REG MaskBlock (MaskBlock)
REG MaskSrcTran (MaskSrcTran)
REG MaskDstTran (MaskDstTran)
REG MaskErr (MaskErr)
REG ClearTfr (ClearTfr)
REG ClearBlock (ClearBlock)
REG ClearSrcTran (ClearSrcTran)
REG ClearDstTran (ClearDstTran)
REG ClearErr (ClearErr)
REG StatusInt (StatusInt)
REG DmaCfgReg (DmaCfgReg)
REG ChEnReg (ChEnReg)
REG Reserved0_CPL (Reserved0_CPL)
REG Reserved0_CPH (Reserved0_CPH)
REG Reserved1_CPL (Reserved1_CPL)
REG Reserved1_CPH (Reserved1_CPH)
REG Reserved0_FPL (Reserved0_FPL)
REG Reserved0_FPH (Reserved0_FPH)
REG Reserved1_FPL (Reserved1_FPL)
REG Reserved1_FPH (Reserved1_FPH)
REG SAI_ERR (SAI_ERR)
REG GLOBAL_CFG (GLOBAL_CFG)
I2C MMIO
I2C Control (IC_CON)
I2C Target Address (IC_TAR)
I2C High Speed Master Mode Code Address (IC_HS_MADDR)
Rx/Tx Data Buffer and Command (IC_DATA_CMD)
Standard Speed I2C Clock SCL High Count (IC_SS_SCL_HCNT)
Standard Speed I2C Clock SCL Low Count (IC_SS_SCL_LCNT)
Fast Speed I2C Clock SCL High Count (IC_FS_SCL_HCNT)
Fast Speed I2C Clock SCL Low Count (IC_FS_SCL_LCNT)
High Speed I2C Clock SCL High Count (IC_HS_SCL_HCNT)
High Speed I2C Clock SCL Low Count (IC_HS_SCL_LCNT)
I2C Interrupt Status Register (IC_INTR_STAT)
Interrupt Mask Register (IC_INTR_MASK)
Raw Interrupt Status (IC_RAW_INTR_STAT)
Receive FIFO Threshold (IC_RX_TL)
Transmit FIFO Threshold (IC_TX_TL)
Clear Combined and Individual Interrupt (IC_CLR_INTR)
Clear RX_UNDER Interrupt (IC_CLR_RX_UNDER)
Clear RX_OVER Interrupt (IC_CLR_RX_OVER)
Clear TX_OVER Interrupt (IC_CLR_TX_OVER)
Clear RD_REQ Interrupt (IC_CLR_RD_REQ)
Clear TX_ABRT Interrupt (IC_CLR_TX_ABRT)
Clear RX_DONE Interrupt (IC_CLR_RX_DONE)
Clear ACTIVITY Interrupt (IC_CLR_ACTIVITY)
Clear STOP_DET Interrupt (IC_CLR_STOP_DET)
Clear START_DET Interrupt (IC_CLR_START_DET)
Clear GEN_CALL Interrupt (IC_CLR_GEN_CALL)
I2C Enable (IC_ENABLE)
I2C Status (IC_STATUS)
I2C Transmit FIFO Level (IC_TXFLR)
Receive FIFO Level (IC_RXFLR)
SDA Hold Time Length (IC_SDA_HOLD)
Transmit Abort Source (IC_TX_ABRT_SOURCE)
DMA Control (IC_DMA_CR)
DMA Transmit Data Level (IC_DMA_TDLR)
Receive Data Level (IC_DMA_RDLR)
SDA Setup (IC_SDA_SETUP)
ACK General Call (IC_ACK_GENERAL_CALL)
I2C Enable Status (IC_ENABLE_STATUS)
SS and FS Spike Suppression Limit (IC_FS_SPKLEN)
HS Spike Suppression Limit (IC_HS_SPKLEN)
I2C PCI Configuration (D21:F0/1/2/3; D25:F0/1
Device Id And Vendor Id Register (DEVVENDID)
Status And Command (STATUSCOMMAND)
Revision Id And Class Code (REVCLASSCODE)
Cache Line Latency Header And Bist (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Subsystem Vendor And Subsystem Id (SUBSYSTEMID)
Expansion Rom Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer Register (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Control And Status Register (PMECTRLSTATUS)
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)
I3C Additional MMIO
REG MULT_BUS_INST_EXT_CAP (MULT_BUS_INST_EXT_CAP)
REG MULT_BUS_INST_CNT (MULT_BUS_INST_CNT)
REG MULT_BUS_INST_OFFSET (MULT_BUS_INST_OFFSET)
REG VND_SPEC_EXT_CAP_2 (VND_SPEC_EXT_CAP_2)
REG RESETS (RESETS)
REG GENERAL (GENERAL)
REG ACTIVELTR (ACTIVELTR)
REG IDLELTR (IDLELTR)
REG SW_SCRATCH_0 (SW_SCRATCH_0)
REG CLOCK_GATE (CLOCK_GATE)
REG DEVIDLE_CONTROL (DEVIDLE_CONTROL)
REG HCI_COMP_VER_OVRD (HCI_COMP_VER_OVRD)
REG I3C_Threshold (I3C_Threshold)
REG Ext_CAP_End (Ext_CAP_End)
I3C DMA Controller
REG CR_SETUP_0 (CR_SETUP_0)
REG IBI_SETUP_0 (IBI_SETUP_0)
REG CHUNK_CONTROL_0 (CHUNK_CONTROL_0)
REG RH_INTR_STATUS_0 (RH_INTR_STATUS_0)
REG RH_INTR_STATUS_ENABLE_0 (RH_INTR_STATUS_ENABLE_0)
REG RH_INTR_SIGNAL_ENABLE_0 (RH_INTR_SIGNAL_ENABLE_0)
REG RH_INTR_FORCE_0 (RH_INTR_FORCE_0)
REG RH_STATUS_0 (RH_STATUS_0)
REG RH_CONTROL_0 (RH_CONTROL_0)
REG RH_OPERATION1_0 (RH_OPERATION1_0)
REG RH_OPERATION2_0 (RH_OPERATION2_0)
REG RH_CMD_RING_BASE_LO_0 (RH_CMD_RING_BASE_LO_0)
REG RH_CMD_RING_BASE_HI_0 (RH_CMD_RING_BASE_HI_0)
REG RH_RESP_RING_BASE_LO_0 (RH_RESP_RING_BASE_LO_0)
REG RH_RESP_RING_BASE_HI_0 (RH_RESP_RING_BASE_HI_0)
REG RH_IBI_STATUS_RING_BASE_LO_0 (RH_IBI_STATUS_RING_BASE_LO_0)
REG RH_IBI_STATUS_RING_BASE_HI_0 (RH_IBI_STATUS_RING_BASE_HI_0)
REG RH_IBI_DATA_RING_BASE_LO_0 (RH_IBI_DATA_RING_BASE_LO_0)
REG RH_IBI_DATA_RING_BASE_HI_0 (RH_IBI_DATA_RING_BASE_HI_0)
REG RHS_CONTROL_0 (RHS_CONTROL_0)
REG RH0_OFFSET_0 (RH0_OFFSET_0)
REG RH1_OFFSET_0 (RH1_OFFSET_0)
REG RH2_OFFSET_0 (RH2_OFFSET_0)
REG RH3_OFFSET_0 (RH3_OFFSET_0)
REG RH4_OFFSET_0 (RH4_OFFSET_0)
REG RH5_OFFSET_0 (RH5_OFFSET_0)
REG RH6_OFFSET_0 (RH6_OFFSET_0)
REG RH7_OFFSET_0 (RH7_OFFSET_0)
REG CR_SETUP_2 (CR_SETUP_2)
REG IBI_SETUP_2 (IBI_SETUP_2)
REG CHUNK_CONTROL_2 (CHUNK_CONTROL_2)
REG RH_INTR_STATUS_2 (RH_INTR_STATUS_2)
REG RH_INTR_STATUS_ENABLE_2 (RH_INTR_STATUS_ENABLE_2)
REG RH_INTR_SIGNAL_ENABLE_2 (RH_INTR_SIGNAL_ENABLE_2)
REG RH_INTR_FORCE_2 (RH_INTR_FORCE_2)
REG RH_STATUS_2 (RH_STATUS_2)
REG RH_CONTROL_2 (RH_CONTROL_2)
REG RH_OPERATION1_2 (RH_OPERATION1_2)
REG RH_OPERATION2_2 (RH_OPERATION2_2)
REG RH_CMD_RING_BASE_LO_2 (RH_CMD_RING_BASE_LO_2)
REG RH_CMD_RING_BASE_HI_2 (RH_CMD_RING_BASE_HI_2)
REG RH_RESP_RING_BASE_LO_2 (RH_RESP_RING_BASE_LO_2)
REG RH_RESP_RING_BASE_HI_2 (RH_RESP_RING_BASE_HI_2)
REG RH_IBI_STATUS_RING_BASE_LO_2 (RH_IBI_STATUS_RING_BASE_LO_2)
REG RH_IBI_STATUS_RING_BASE_HI_2 (RH_IBI_STATUS_RING_BASE_HI_2)
REG RH_IBI_DATA_RING_BASE_LO_2 (RH_IBI_DATA_RING_BASE_LO_2)
REG RH_IBI_DATA_RING_BASE_HI_2 (RH_IBI_DATA_RING_BASE_HI_2)
REG RHS_CONTROL_1 (RHS_CONTROL_1)
REG RH0_OFFSET_1 (RH0_OFFSET_1)
REG RH1_OFFSET_1 (RH1_OFFSET_1)
REG RH2_OFFSET_1 (RH2_OFFSET_1)
REG RH3_OFFSET_1 (RH3_OFFSET_1)
REG RH4_OFFSET_1 (RH4_OFFSET_1)
REG RH5_OFFSET_1 (RH5_OFFSET_1)
REG RH6_OFFSET_1 (RH6_OFFSET_1)
REG RH7_OFFSET_1 (RH7_OFFSET_1)
REG CR_SETUP_1 (CR_SETUP_1)
REG IBI_SETUP_1 (IBI_SETUP_1)
REG CHUNK_CONTROL_1 (CHUNK_CONTROL_1)
REG RH_INTR_STATUS_1 (RH_INTR_STATUS_1)
REG RH_INTR_STATUS_ENABLE_1 (RH_INTR_STATUS_ENABLE_1)
REG RH_INTR_SIGNAL_ENABLE_1 (RH_INTR_SIGNAL_ENABLE_1)
REG RH_INTR_FORCE_1 (RH_INTR_FORCE_1)
REG RH_STATUS_1 (RH_STATUS_1)
REG RH_CONTROL_1 (RH_CONTROL_1)
REG RH_OPERATION1_1 (RH_OPERATION1_1)
REG RH_OPERATION2_1 (RH_OPERATION2_1)
REG RH_CMD_RING_BASE_LO_1 (RH_CMD_RING_BASE_LO_1)
REG RH_CMD_RING_BASE_HI_1 (RH_CMD_RING_BASE_HI_1)
REG RH_RESP_RING_BASE_LO_1 (RH_RESP_RING_BASE_LO_1)
REG RH_RESP_RING_BASE_HI_1 (RH_RESP_RING_BASE_HI_1)
REG RH_IBI_STATUS_RING_BASE_LO_1 (RH_IBI_STATUS_RING_BASE_LO_1)
REG RH_IBI_STATUS_RING_BASE_HI_1 (RH_IBI_STATUS_RING_BASE_HI_1)
REG RH_IBI_DATA_RING_BASE_LO_1 (RH_IBI_DATA_RING_BASE_LO_1)
REG RH_IBI_DATA_RING_BASE_HI_1 (RH_IBI_DATA_RING_BASE_HI_1)
REG CR_SETUP_3 (CR_SETUP_3)
REG IBI_SETUP_3 (IBI_SETUP_3)
REG CHUNK_CONTROL_3 (CHUNK_CONTROL_3)
REG RH_INTR_STATUS_3 (RH_INTR_STATUS_3)
REG RH_INTR_STATUS_ENABLE_3 (RH_INTR_STATUS_ENABLE_3)
REG RH_INTR_SIGNAL_ENABLE_3 (RH_INTR_SIGNAL_ENABLE_3)
REG RH_INTR_FORCE_3 (RH_INTR_FORCE_3)
REG RH_STATUS_3 (RH_STATUS_3)
REG RH_CONTROL_3 (RH_CONTROL_3)
REG RH_OPERATION1_3 (RH_OPERATION1_3)
REG RH_OPERATION2_3 (RH_OPERATION2_3)
REG RH_CMD_RING_BASE_LO_3 (RH_CMD_RING_BASE_LO_3)
REG RH_CMD_RING_BASE_HI_3 (RH_CMD_RING_BASE_HI_3)
REG RH_RESP_RING_BASE_LO_3 (RH_RESP_RING_BASE_LO_3)
REG RH_RESP_RING_BASE_HI_3 (RH_RESP_RING_BASE_HI_3)
REG RH_IBI_STATUS_RING_BASE_LO_3 (RH_IBI_STATUS_RING_BASE_LO_3)
REG RH_IBI_STATUS_RING_BASE_HI_3 (RH_IBI_STATUS_RING_BASE_HI_3)
REG RH_IBI_DATA_RING_BASE_LO_3 (RH_IBI_DATA_RING_BASE_LO_3)
REG RH_IBI_DATA_RING_BASE_HI_3 (RH_IBI_DATA_RING_BASE_HI_3)
I3C MMIO
REG HCI_VERSION (HCI_VERSION)
REG DEVICE_CONTROL (DEVICE_CONTROL)
REG DEVICE_ADDR (DEVICE_ADDR)
REG DEVICE_CAPABILITIES (DEVICE_CAPABILITIES)
REG RESET_CTRL (RESET_CTRL)
REG PRESENT_STATE (PRESENT_STATE)
REG INTR_STATUS (INTR_STATUS)
REG INTR_STATUS_ENABLE (INTR_STATUS_ENABLE)
REG INTR_SIGNAL_ENABLE (INTR_SIGNAL_ENABLE)
REG INTR_FORCE (INTR_FORCE)
REG DAT_SECTION_OFFSET (DAT_SECTION_OFFSET)
REG DCT_SECTION_OFFSET (DCT_SECTION_OFFSET)
REG RING_HEADERS_SECTION_OFFSET (RING_HEADERS_SECTION_OFFSET)
REG PIO_SECTION_OFFSET (PIO_SECTION_OFFSET)
REG EXTCAPS_SECTION_OFFSET (EXTCAPS_SECTION_OFFSET)
REG IBI_NOTIFY_CTRL (IBI_NOTIFY_CTRL)
REG DEV_ADDR_TABLE1_LOC1 (DEV_ADDR_TABLE1_LOC1)
REG DEV_ADDR_TABLE1_LOC2 (DEV_ADDR_TABLE1_LOC2)
REG DEV_ADDR_TABLE2_LOC1 (DEV_ADDR_TABLE2_LOC1)
REG DEV_ADDR_TABLE2_LOC2 (DEV_ADDR_TABLE2_LOC2)
REG DEV_ADDR_TABLE3_LOC1 (DEV_ADDR_TABLE3_LOC1)
REG DEV_ADDR_TABLE3_LOC2 (DEV_ADDR_TABLE3_LOC2)
REG DEV_ADDR_TABLE4_LOC1 (DEV_ADDR_TABLE4_LOC1)
REG DEV_ADDR_TABLE4_LOC2 (DEV_ADDR_TABLE4_LOC2)
REG DEV_ADDR_TABLE5_LOC1 (DEV_ADDR_TABLE5_LOC1)
REG DEV_ADDR_TABLE5_LOC2 (DEV_ADDR_TABLE5_LOC2)
REG DEV_ADDR_TABLE6_LOC1 (DEV_ADDR_TABLE6_LOC1)
REG DEV_ADDR_TABLE6_LOC2 (DEV_ADDR_TABLE6_LOC2)
REG DEV_ADDR_TABLE7_LOC1 (DEV_ADDR_TABLE7_LOC1)
REG DEV_ADDR_TABLE7_LOC2 (DEV_ADDR_TABLE7_LOC2)
REG DEV_ADDR_TABLE8_LOC1 (DEV_ADDR_TABLE8_LOC1)
REG DEV_ADDR_TABLE8_LOC2 (DEV_ADDR_TABLE8_LOC2)
REG COMMAND_QUEUE_PORT (COMMAND_QUEUE_PORT)
REG RESPONSE_QUEUE_PORT (RESPONSE_QUEUE_PORT)
REG DATA_PORT (DATA_PORT)
REG IBI_PORT (IBI_PORT)
REG QUEUE_THLD_CTRL (QUEUE_THLD_CTRL)
REG DATA_BUFFER_THLD_CTRL (DATA_BUFFER_THLD_CTRL)
REG QUEUE_SIZE_CTRL (QUEUE_SIZE_CTRL)
REG DEV_CHAR_TABLE1_LOC1 (DEV_CHAR_TABLE1_LOC1)
REG DEV_CHAR_TABLE1_LOC2 (DEV_CHAR_TABLE1_LOC2)
REG DEV_CHAR_TABLE1_LOC3 (DEV_CHAR_TABLE1_LOC3)
REG DEV_CHAR_TABLE1_LOC4 (DEV_CHAR_TABLE1_LOC4)
REG DEV_CHAR_TABLE2_LOC1 (DEV_CHAR_TABLE2_LOC1)
REG DEV_CHAR_TABLE2_LOC2 (DEV_CHAR_TABLE2_LOC2)
REG DEV_CHAR_TABLE2_LOC3 (DEV_CHAR_TABLE2_LOC3)
REG DEV_CHAR_TABLE2_LOC4 (DEV_CHAR_TABLE2_LOC4)
REG DEV_CHAR_TABLE3_LOC1 (DEV_CHAR_TABLE3_LOC1)
REG DEV_CHAR_TABLE3_LOC2 (DEV_CHAR_TABLE3_LOC2)
REG DEV_CHAR_TABLE3_LOC3 (DEV_CHAR_TABLE3_LOC3)
REG DEV_CHAR_TABLE3_LOC4 (DEV_CHAR_TABLE3_LOC4)
REG DEV_CHAR_TABLE4_LOC1 (DEV_CHAR_TABLE4_LOC1)
REG DEV_CHAR_TABLE4_LOC2 (DEV_CHAR_TABLE4_LOC2)
REG DEV_CHAR_TABLE4_LOC3 (DEV_CHAR_TABLE4_LOC3)
REG DEV_CHAR_TABLE4_LOC4 (DEV_CHAR_TABLE4_LOC4)
REG DEV_CHAR_TABLE5_LOC1 (DEV_CHAR_TABLE5_LOC1)
REG DEV_CHAR_TABLE5_LOC2 (DEV_CHAR_TABLE5_LOC2)
REG DEV_CHAR_TABLE5_LOC3 (DEV_CHAR_TABLE5_LOC3)
REG DEV_CHAR_TABLE5_LOC4 (DEV_CHAR_TABLE5_LOC4)
REG DEV_CHAR_TABLE6_LOC1 (DEV_CHAR_TABLE6_LOC1)
REG DEV_CHAR_TABLE6_LOC2 (DEV_CHAR_TABLE6_LOC2)
REG DEV_CHAR_TABLE6_LOC3 (DEV_CHAR_TABLE6_LOC3)
REG DEV_CHAR_TABLE6_LOC4 (DEV_CHAR_TABLE6_LOC4)
REG DEV_CHAR_TABLE7_LOC1 (DEV_CHAR_TABLE7_LOC1)
REG DEV_CHAR_TABLE7_LOC2 (DEV_CHAR_TABLE7_LOC2)
REG DEV_CHAR_TABLE7_LOC3 (DEV_CHAR_TABLE7_LOC3)
REG DEV_CHAR_TABLE7_LOC4 (DEV_CHAR_TABLE7_LOC4)
REG DEV_CHAR_TABLE8_LOC1 (DEV_CHAR_TABLE8_LOC1)
REG DEV_CHAR_TABLE8_LOC2 (DEV_CHAR_TABLE8_LOC2)
REG DEV_CHAR_TABLE8_LOC3 (DEV_CHAR_TABLE8_LOC3)
REG DEV_CHAR_TABLE8_LOC4 (DEV_CHAR_TABLE8_LOC4)
REG HW_IDENTIFICATION_HEADER (HW_IDENTIFICATION_HEADER)
REG COMP_MANUFACTURER (COMP_MANUFACTURER)
REG COMP_VERSION (COMP_VERSION)
REG COMP_TYPE (COMP_TYPE)
REG BUS_TIMING_HEADER (BUS_TIMING_HEADER)
REG SCL_I3C_OD_TIMING (SCL_I3C_OD_TIMING)
REG SCL_I3C_PP_TIMING (SCL_I3C_PP_TIMING)
REG SCL_I2C_FM_TIMING (SCL_I2C_FM_TIMING)
REG SCL_I2C_FMP_TIMING (SCL_I2C_FMP_TIMING)
REG SCL_I2C_SS_TIMING (SCL_I2C_SS_TIMING)
REG SCL_EXT_LCNT_TIMING (SCL_EXT_LCNT_TIMING)
REG SCL_EXT_TERMN_LCNT_TIMING (SCL_EXT_TERMN_LCNT_TIMING)
REG SDA_HOLD_SWITCH_DLY_TIMING (SDA_HOLD_SWITCH_DLY_TIMING)
REG BUS_FREE_TIMING (BUS_FREE_TIMING)
REG DS_EXTCAP_HEADER (DS_EXTCAP_HEADER)
REG QUEUE_STATUS_LEVEL (QUEUE_STATUS_LEVEL)
REG DATA_BUFFER_STATUS_LEVEL (DATA_BUFFER_STATUS_LEVEL)
REG PRESENT_STATE_DEBUG (PRESENT_STATE_DEBUG)
REG MASTER_EXT_HEADER (MASTER_EXT_HEADER)
REG MASTER_CONFIG (MASTER_CONFIG)
I3C PCI Configuration (D17:F0/2)
Device Id And Vendor Id Register (DEVVENDID)
Status And Command (STATUSCOMMAND)
Revision Id And Class Code (REVCLASSCODE)
Cache Line Latency Header And Bist (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Subsystem Vendor And Subsystem Id (SUBSYSTEMID)
Expansion Rom Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer Register (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Control And Status Register (PMECTRLSTATUS)
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)
IDE Redirection (IDE-R) PCI Configuration (D22:F2)
Device ID And Vendor ID (IDE_HOST_DID_VID)
Status And Command (IDE_HOST_STS_CMD)
Class Code And Revision ID (IDE_HOST_CC_RID)
BIST, Header Type, Latency Timer, And Cache Line Size (IDE_HOST_BIST_HTYPE_LT_CLS)
IDE Primary Command Block IO BAR (IDE_HOST_PCMDIOBAR)
IDE Primary Control Block IO BAR (IDE_HOST_PCTLIOBAR)
IDE Secondary Command Block IO BAR (IDE_HOST_SCMDIOBAR)
IDE Secondary Control Block IO BAR (IDE_HOST_SCTLIOBAR)
IDE Bus Initiator Block IO BAR (IDE_HOST_BMIOBAR)
Cardbus CIS Pointer (IDE_HOST_CCP)
Subsystem ID And Subsystem Vendor ID (IDE_HOST_SID_SVID)
Expansion ROM Base Address (IDE_HOST_XRBAR)
Capabilities List Pointer (IDE_HOST_CAPP)
Maximum Latency, Minimum Grant, Interrupt Pin And Interrupt Line (IDE_HOST_MAXL_MING_INTP_INTL)
MSI Message Control, Next Pointer And Capability ID (IDE_HOST_MSIMC_MSINP_MSICID)
MSI Message Address (IDE_HOST_MSIMA)
MSI Message Upper Address (IDE_HOST_MSIMUA)
MSI Message Data (IDE_HOST_MSIMD)
Power Management Capabilities, Next Pointer And Capability ID (IDE_HOST_PMCAP_PMNP_PMCID)
Power Management Data, Control/Status Register Bridge Support Extensions, Control And Status (IDE_HOST_PMD_PMCSRBSE_PMCSR)
Process Stepping Information (IDE_HOST_PSI)
Integrated GbE Configuration (D31:F6)
GbE Vendor and Device Identification Register (DMI_CONFIG0)
PCI Command & Status Register (DMI_CONFIG1)
Revision Identification & Class Code Register (DMI_CONFIG2)
Cache Line Size Primary Latency Timer & Header Type Register (DMI_CONFIG3)
Memory Base Address Register A (DMI_CONFIG4)
Memory Base Address Register B (DMI_CONFIG5)
Subsystem Vendor & Subsytem ID (DMI_CONFIG11)
Expansion ROM Base Address Register (DMI_CONFIG12)
Capabilities List Pointer Register (DMI_CONFIG13)
Interrupt Information & Maximum Latency/Minimum GrantRegister (DMI_CONFIG15)
Integrated GbE Memory Mapped I/O
Gigabit Ethernet Capabilities and Status at Offset 0h (GBECSR_00)
Gigabit Ethernet Capabilities and Status at Offset 18h (GBECSR_18)
Gigabit Ethernet Capabilities and Status at Offset 20h (GBECSR_20)
Gigabit Ethernet Capabilities and Status at Offset F00h (GBECSR_F00)
Gigabit Ethernet Capabilities and Status at Offset F10h (GBECSR_F10)
Gigabit Ethernet Capabilities and Status at Offset 5400h (GBECSR_5400)
Gigabit Ethernet Capabilities and Status at Offset 5404h (GBECSR_5404)
Gigabit Ethernet Capabilities and Status at Offset 5800h (GBECSR_5800)
Gigabit Ethernet Capabilities and Status at Offset 5B54h (GBECSR_5B54)
Intel® Management Interface (MEI) PCI Configuration
HECI ID (HECI1_ID)
HECI Command (HECI1_CMD)
HECI Status (HECI1_STS)
Revision ID And Class Code (HECI1_RID_CC)
Cache Line Size (HECI1_CLS)
Initiator Latency Timer (HECI1_MLT)
Header Type (HECI1_HTYPE)
Built In Self-Test (HECI1_BIST)
HECI MMIO Base Address Low (HECI1_MMIO_MBAR_LO)
HECI MMIO Base Address High (HECI1_MMIO_MBAR_HI)
Sub System Identifiers (HECI1_SS)
Capabilities Pointer (HECI1_CAP)
Interrupt Information (HECI1_INTR)
Minimum Grant (HECI1_MGNT)
Maximum Latency (HECI1_MLAT)
Host Firmware Status (HECI1_HFS)
Miscellaneous Shadow (HECI1_MISC_SHDW)
General Status Shadow 1 (HECI1_GS_SHDW1)
Host General Status (HECI1_H_GS1)
PCI Power Management Capability ID (HECI1_PID)
PCI Power Management Capabilities (HECI1_PC)
PCI Power Management Control And Status (HECI1_PMCS)
General Status Shadow 2 (HECI1_GS_SHDW2)
General Status Shadow 3 (HECI1_GS_SHDW3)
General Status Shadow 4 (HECI1_GS_SHDW4)
General Status Shadow 5 (HECI1_GS_SHDW5)
Host General Status 2 (HECI1_H_GS2)
Host General Status 3 (HECI1_H_GS3)
Message Signaled Interrupt Identifiers (HECI1_MID)
Message Signaled Interrupt Message Control (HECI1_MC)
Message Signaled Interrupt Message Address (HECI1_MA)
Message Signaled Interrupt Upper Address (HECI1_MUA)
Message Signaled Interrupt Message Data (HECI1_MD)
HECI Interrupt Delivery Mode (HECI1_HIDM)
Vendor Specific Capability Register (HECI1_VSCR)
Vendor Specific Extended Capability Register (HECI1_VSEC)
SW LTR Pointer Register (HECI1_SWLTRPTR)
Device Idle Pointer Register (HECI1_DEVIDLEPTR)
Device Idle Power On Latency (HECI1_DEVIDLEPOL)
DevIdle Power Control Enabled Register (HECI1_PWRCTRLEN)
Host Extend Register Status (HECI1_HERS)
Host Extend Register DW1 (HECI1_HER1)
Host Extend Register DW2 (HECI1_HER2)
Host Extend Register DW3 (HECI1_HER3)
Host Extend Register DW4 (HECI1_HER4)
Host Extend Register DW5 (HECI1_HER5)
Host Extend Register DW6 (HECI1_HER6)
Host Extend Register DW7 (HECI1_HER7)
Host Extend Register DW8 (HECI1_HER8)
Intel® Trace Hub PCI Configuration (D31:F7)
Vendor ID Register (VID)
Command Register (CMD)
Class Code Register (RID)
Header Type Register (HT)
MSC Trace Buffer Lower BAR (MTB_LBAR)
MSC Trace Buffer Upper BAR (MTB_UBAR)
Software Lower BAR (SW_LBAR)
Software Upper BAR (SW_UBAR)
RTIT Lower BAR (RTIT_LBAR)
RTIT Upper BAR (RTIT_UBAR)
Subsystem Vendor ID (SVID)
Capabilities Pointer (CAP)
Interrupt Line (INTL)
MSI Capability ID (MSICID)
MSI Lower Message Address (MSILMA)
MSI Upper Message Address (MSIUMA)
MSI Message Data (MSIMD)
Firmware Lower Bar (FW_LBAR)
Firmware Upper Bar (FW_UBAR)
NPK Device Specific Control (NPKDSC)
Power Control Enable Register (DEVIDLEPCE)
Intel® Trusted Execution Technology Configuration Registers
Status Register (STS)
Error Status Register (ESTS)
Crash Register (CRASH)
SPAD Register (SPAD_DONE)
DID Register (DIDVID)
EMC Version Numer Register (VER_EMIF)
Unlock Memory Config Command (CMD_UNLOCK_MEMCONFIG)
SINIT Memory Base Address (SINIT_MEMORY_BASE)
SINIT Memory Size Register (SINIT_MEMORY_SIZE)
SVMM Join Base Address (SVMM_JOIN)
Heap Base (HEAP_BASE)
Heap Size (HEAP_SIZE)
DMA Protected Range (DPR)
SCRATCHPAD6 (LT_SCRATCHPAD6)
Open Locality 1 Command (CMD_OPEN_LOCALITY1)
Open Locality 2 Command (CMD_OPEN_LOCALITY2)
Intergrated Sensor Hub (ISH) PCI Configuration (D18:F0)
Device Id And Vendor Id Register (DEVVENDID)
Status And Command (STATUSCOMMAND)
Revision Id And Class Code (REVCLASSCODE)
Cache Line Latency Header And Bist (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Subsystem Vendor And Subsystem Id (SUBSYSTEMID)
Expansion Rom Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Capability Id (POWERCAPID)
Power Management Control And Status Register (PMECTRLSTATUS)
Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD)
Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG)
Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG)
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Input Register (GEN_INPUT_REG)
Interrupt I/O
Master Initialization Command Word 1 (MICW1)
Master Operational Control Word 2 (MOCW2)
Master Operational Control Word 3 (MOCW3)
Master Initialization Command Word 2 (MICW2)
Master Initialization Command Word 3 (MICW3)
Master Initialization Command Word 4 (MICW4)
Master Operational Control Word 1 (MOCW1)
Slave Initialization Command Word 1 (SICW1)
Slave Operational Control Word 2 (SOCW2)
Slave Operational Control Word 3 (SOCW3)
Slave Initialization Command Word 2 (SICW2)
Slave Initialization Command Word 3 (SICW3)
Slave Initialization Command Word 4 (SICW4)
Slave Operational Control Word 1 (SOCW1)
Master Edge/Level Control (ELCR1)
Slave Edge/Level Control (ELCR2)
Interrupt PCR
PIRQA Routing Control (PARC)
Message Decoder Control (MSGDC)
PCI Interrupt Route 0 (PIR0)
PCI Interrupt Route 1 (PIR1)
PCI Interrupt Route 2 (PIR2)
PCI Interrupt Route 3 (PIR3)
PCI Interrupt Route 4 (PIR4)
PCI Interrupt Route 5 (PIR5)
PCI Interrupt Route 6 (PIR6)
PCI Interrupt Route 7 (PIR7)
PCI Interrupt Route 8 (PIR8)
PCI Interrupt Route 9 (PIR9)
PCI Interrupt Route 10 (PIR10)
PCI Interrupt Route 11 (PIR11)
PCI Interrupt Route 12 (PIR12)
PCI Interrupt Route 13 (PIR13)
PCI Interrupt Route 14 (PIR14)
PCI Interrupt Route 15 (PIR15)
PCI Interrupt Route 16 (PIR16)
PCI Interrupt Route 17 (PIR17)
PCI Interrupt Route 18 (PIR18)
PCI Interrupt Route 19 (PIR19)
PCI Interrupt Route 20 (PIR20)
PCI Interrupt Route 21 (PIR21)
PCI Interrupt Route 22 (PIR22)
PCI Interrupt Route 23 (PIR23)
PCI Interrupt Route 24 (PIR24)
PCI Interrupt Route 25 (PIR25)
PCI Interrupt Route 26 (PIR26)
PCI Interrupt Route 27 (PIR27)
PCI Interrupt Route 28 (PIR28)
PCI Interrupt Route 29 (PIR29)
PCI Interrupt Route 30 (PIR30)
PCI Interrupt Route 31 (PIR31)
General Interrupt Control (GIC)
Interrupt Polarity Control 0 (IPC0)
Interrupt Polarity Control 1 (IPC1)
Interrupt Polarity Control 2 (IPC2)
Interrupt Polarity Control 3 (IPC3)
Interrupt Blocking Control (IBC)
Interrupt Edge-Trigger Extension 0 (IETE0)
Interrupt Edge-Trigger Extension 1 (IETE1)
Interrupt Edge-Trigger Extension 2 (IETE2)
Interrupt Edge-Trigger Extension 3 (IETE3)
ITSS Power Reduction Control (ITSSPRC)
SIDE Clock Timing (SIDECT)
IPCI Clock Timing (IPCICT)
PGCB Clock Timing (PGCBCT)
Uncorrectable Error Mask (UEM)
Uncorrectable Error Severity (UEV)
Correctable Error Mask (CEM)
NMI Control (NMI)
Master Message Control (MMC)
IO Trap
PSTH Control Register (PSTHCTL)
Trap Status Register (TRPSTS)
Trapped Cycle Register (TRPCYC1)
Trapped Cycle Register (TRPCYC2)
Trapped Write Data Register (TRPWRDATA1)
Trapped Write Data Register (TRPWRDATA2)
I/O Trap Registers 1 (IOTRP1_1)
I/O Trap Registers 1 (IOTRP1_2)
I/O Trap Registers 2 (IOTRP2_1)
I/O Trap Registers 2 (IOTRP2_2)
I/O Trap Registers 3 (IOTRP3_1)
I/O Trap Registers 3 (IOTRP3_2)
I/O Trap Registers 4 (IOTRP4_1)
I/O Trap Registers 4 (IOTRP4_2)
IOM Register
Version Register (VER_REG_0_0_0_VTDBAR)
Capability Register (CAP_REG_0_0_0_VTDBAR)
Extended Capability Register (ECAP_REG_0_0_0_VTDBAR)
Global Command Register (GCMD_REG_0_0_0_VTDBAR)
Global Status Register (GSTS_REG_0_0_0_VTDBAR)
Context Command Register (CCMD_REG_0_0_0_VTDBAR)
Fault Status Register (FSTS_REG_0_0_0_VTDBAR)
Fault Event Control Register (FECTL_REG_0_0_0_VTDBAR)
Fault Event Data Register (FEDATA_REG_0_0_0_VTDBAR)
Fault Event Address Register (FEADDR_REG_0_0_0_VTDBAR)
Fault Event Upper Address Register (FEUADDR_REG_0_0_0_VTDBAR)
Advanced Fault Log Register (AFLOG_REG_0_0_0_VTDBAR)
Protected Memory Enable Register (PMEN_REG_0_0_0_VTDBAR)
Protected Low Memory Base Register (PLMBASE_REG_0_0_0_VTDBAR)
Protected Low-Memory Limit Register (PLMLIMIT_REG_0_0_0_VTDBAR)
Protected High-Memory Base Register (PHMBASE_REG_0_0_0_VTDBAR)
Protected High-Memory Limit Register (PHMLIMIT_REG_0_0_0_VTDBAR)
Invalidation Queue Head Register (IQH_REG_0_0_0_VTDBAR)
Invalidation Queue Tail Register (IQT_REG_0_0_0_VTDBAR)
Invalidation Queue Address Register (IQA_REG_0_0_0_VTDBAR)
Invalidation Completion Status Register (ICS_REG_0_0_0_VTDBAR)
Invalidation Event Control Register (IECTL_REG_0_0_0_VTDBAR)
Invalidation Event Data Register (IEDATA_REG_0_0_0_VTDBAR)
Invalidation Event Address Register (IEADDR_REG_0_0_0_VTDBAR)
Invalidation Event Upper Address Register (IEUADDR_REG_0_0_0_VTDBAR)
IQ Error Info register (IQERCD_REG_0_0_0_VTDBAR)
Interrupt Remapping Table Address Register (IRTA_REG_0_0_0_VTDBAR)
Page Request Queue Head Register (PQH_REG_0_0_0_VTDBAR)
Page Request Queue Tail Register (PQT_REG_0_0_0_VTDBAR)
Page Request Queue Address Register (PQA_REG_0_0_0_VTDBAR)
Page Request Status Register (PRS_REG_0_0_0_VTDBAR)
Page Request Event Control Register (PECTL_REG_0_0_0_VTDBAR)
Page Request Event Data Register (PEDATA_REG_0_0_0_VTDBAR)
Page Request Event Address Register (PEADDR_REG_0_0_0_VTDBAR)
Page Request Event Upper Address Register (PEUADDR_REG_0_0_0_VTDBAR)
MTRR Capability Register (MTRRCAP_0_0_0_VTDBAR)
MTRR Default Type Register (MTRRDEFAULT_0_0_0_VTDBAR)
Fixed-Range MTRR Format 64K-00000 (MTRR_FIX64K_00000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 16K-80000 (MTRR_FIX16K_80000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 16K-A0000 (MTRR_FIX16K_A0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-C0000 (MTRR_FIX4K_C0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-C8000 (MTRR_FIX4K_C8000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-D0000 (MTRR_FIX4K_D0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-D8000 (MTRR_FIX4K_D8000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-E0000 (MTRR_FIX4K_E0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-E8000 (MTRR_FIX4K_E8000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-F0000 (MTRR_FIX4K_F0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-F8000 (MTRR_FIX4K_F8000_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 0 (MTRR_PHYSBASE0_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 0 (MTRR_PHYSMASK0_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 1 (MTRR_PHYSBASE1_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 1 (MTRR_PHYSMASK1_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 2 (MTRR_PHYSBASE2_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 2 (MTRR_PHYSMASK2_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 3 (MTRR_PHYSBASE3_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 3 (MTRR_PHYSMASK3_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 4 (MTRR_PHYSBASE4_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 4 (MTRR_PHYSMASK4_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 5 (MTRR_PHYSBASE5_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 5 (MTRR_PHYSMASK5_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 6 (MTRR_PHYSBASE6_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 6 (MTRR_PHYSMASK6_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 7 (MTRR_PHYSBASE7_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 7 (MTRR_PHYSMASK7_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 8 (MTRR_PHYSBASE8_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 8 (MTRR_PHYSMASK8_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 9 (MTRR_PHYSBASE9_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 9 (MTRR_PHYSMASK9_REG_0_0_0_VTDBAR)
Performance Monitoring Capabilities (PERFCAP_0_0_0_VTDBAR)
Performance Monitoring Configuration Offset (PERFCFGOFF_0_0_0_VTDBAR)
Performance Monitoring Freeze Offset (PERFFRZOFF_0_0_0_VTDBAR)
Performance Monitoring Overflow Offset (PERFOVFOFF_0_0_0_VTDBAR)
Performance Monitoring Counter Offset (PERFCNTOFF_0_0_0_VTDBAR)
Performance Interrupt Status (PERFINTRSTS_0_0_0_VTDBAR)
Performance Interrupt Control (PERFINTRCTL_0_0_0_VTDBAR)
Performance Interrupt Data (PERFINTRDATA_0_0_0_VTDBAR)
Performance Interrupt Address (PERFINTRADDR_0_0_0_VTDBAR)
Performance Interrupt Upper Address (PERFINTRUADDR_0_0_0_VTDBAR)
Performance Monitoring Event Capabilities (PERFEVNTCAP0_0_0_0_VTDBAR)
Performance Monitoring Event Capabilities (PERFEVNTCAP1_0_0_0_VTDBAR)
Performance Monitoring Event Capabilities (PERFEVNTCAP2_0_0_0_VTDBAR)
Performance Monitoring Event Capabilities (PERFEVNTCAP3_0_0_0_VTDBAR)
Performance Monitoring Event Capabilities (PERFEVNTCAP4_0_0_0_VTDBAR)
Enhanced Command (ECMD_0_0_0_VTDBAR)
Enhanced Command Response (ERESP_0_0_0_VTDBAR)
Enhanced Command Status (ESTS0_0_0_0_VTDBAR)
Enhanced Command Status (ESTS1_0_0_0_VTDBAR)
Enhanced Command Capabilities (ECMD_CAP0_0_0_0_VTDBAR)
Enhanced Command Capabilities (ECMD_CAP1_0_0_0_VTDBAR)
Enhanced Command Capabilities (ECMD_CAP2_0_0_0_VTDBAR)
Enhanced Command Capabilities (ECMD_CAP3_0_0_0_VTDBAR)
Fault Recording Register Low [0] (FRCDL_REG_0_0_0_VTDBAR)
Fault Recording Register High [0] (FRCDH_REG_0_0_0_VTDBAR)
Invalidate Address Register (IVA_REG_0_0_0_VTDBAR)
IOTLB Invalidate Register (IOTLB_REG_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR0_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR0_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR0_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR0_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR0_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP0_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR1_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR1_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR1_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR1_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR1_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP1_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR2_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR2_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR2_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR2_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR2_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP2_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR3_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR3_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR3_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR3_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR3_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP3_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG4_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR4_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR4_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR4_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR4_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR4_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP4_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG5_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR5_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR5_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR5_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR5_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR5_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP5_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG6_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR6_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR6_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR6_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR6_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR6_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP6_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG7_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR7_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR7_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR7_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR7_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR7_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP7_0_0_0_VTDBAR)
Performance Monitoring Counter Event Capabilities (PERFCNTRCAP7_EG0_0_0_0_VTDBAR)
Performance Monitoring Freeze (PERFFRZ0_0_0_0_VTDBAR)
Performance Monitoring Overflow Status (PERFOVFSTS0_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR0_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR1_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR2_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR3_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR4_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR5_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR6_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR7_0_0_0_VTDBAR)
Keyboard and Text (KT) Redirection PCI Configuration (D22:F3)
Device ID And Vendor ID (KT_HOST_DID_VID)
Status And Command (KT_HOST_STS_CMD)
Class Code And Revision ID (KT_HOST_CC_RID)
BIST, Header Type, Latency Timer, And Cache Line Size (KT_HOST_BIST_HTYPE_LT_CLS)
KT IO BAR (KT_HOST_IOBAR)
KT Memory BAR (KT_HOST_MEMBAR)
Cardbus CIS Pointer (KT_HOST_CCP)
Subsystem ID And Subsystem Vendor ID (KT_HOST_SID_SVID)
Expansion ROM Base Address (KT_HOST_XRBAR)
Capabilities List Pointer (KT_HOST_CAPP)
Maximum Latency, Minimum Grant, Interrupt Pin And Interrupt Line (KT_HOST_MAXL_MING_INTP_INTL)
MSI Message Control, Next Pointer And Capability ID (KT_HOST_MSIMC_MSINP_MSICID)
MSI Message Address (KT_HOST_MSIMA)
MSI Message Upper Address (KT_HOST_MSIMUA)
MSI Message Data (KT_HOST_MSIMD)
Power Management Capabilities, Next Pointer And Capability ID (KT_HOST_PMCAP_PMNP_PMCID)
Power Management Data, Control/Status Register Bridge Support Extensions, Control And Status (KT_HOST_PMD_PMCSRBSE_PMCSR)
p2sb cfg
PCI Identifier (PCIID)
PCI Command (PCICMD)
PCI Status (PCISTS)
Revision ID (PCIRID_CC)
PCI Header Type (PCIHTYPE)
Sideband Register Access BAR (SBREG_BAR)
Sideband Register BAR High DWORD (SBREG_BARH)
PCI Subsystem Identifiers (PCIHSS)
PCI Capabilities Pointer (CAPPTR)
High Performance Event Timer Configuration (HPTC)
IOxAPIC Configuration (IOAC)
IOxAPIC Bus:Device:Function (IBDF)
HPET Bus:Device:Function (HBDF)
PCI Express Capability List Register (EXPCAPLST)
PCI Express Capabilities Register (EXPCAP)
Device Capabilities Register (DEVCAP)
Device Control Register (DEVCTL)
Device Status Register (DEVSTS)
Link Capabilities Register (LNKCAP)
Link Control Register (LNKCTL)
Link Status Register (LNKSTS)
SBI Address (SBIADDR)
SBI Data (SBIDATA)
SBI Status (SBISTAT)
SBI Routing Identification (SBIRID)
SBI Extended Address (SBIEXTADDR)
P2SB Control (P2SBC)
Power Control Enable (PCE)
Unsupported Request Error Status (URES)
Unsupported Request Error Control (UREC)
Sideband Register Posted 0 (SBREGPOSTED0)
Sideband Register Posted 1 (SBREGPOSTED1)
Sideband Register Posted 2 (SBREGPOSTED2)
Sideband Register Posted 3 (SBREGPOSTED3)
Sideband Register Posted 4 (SBREGPOSTED4)
Sideband Register Posted 5 (SBREGPOSTED5)
Sideband Register Posted 6 (SBREGPOSTED6)
Sideband Register Posted 7 (SBREGPOSTED7)
Endpoint Mask 0 (EPMASK0)
Endpoint Mask 1 (EPMASK1)
Endpoint Mask 2 (EPMASK2)
Endpoint Mask 3 (EPMASK3)
Endpoint Mask 4 (EPMASK4)
Endpoint Mask 5 (EPMASK5)
Endpoint Mask 6 (EPMASK6)
Endpoint Mask 7 (EPMASK7)
PCI Express* (PCIe*) Congifuration (D28:F0/1/2/3/4/5/6/7)
PCIE Identifiers (ID)
Device Command (CMD)
Primary Status (PSTS)
Revision ID (RID_CC)
Cache Line Size (CLS)
Primary Latency Timer (PLT)
Header Type (HTYPE)
Base Address Register 0 (BAR0)
Base Address Register 1 (BAR1)
Bus Numbers (BNUM_SLT)
I/O Base And Limit (IOBL)
Secondary Status (SSTS)
Memory Base And Limit (MBL)
Prefetchable Memory Base And Limit (PMBL)
Prefetchable Memory Base Upper 32 Bits (PMBU32)
Prefetchable Memory Limit Upper 32 Bits (PMLU32)
Capabilities List Pointer (CAPP)
Interrupt Information Byte 0 (INTRB0)
Interrupt Information Byte 1 (INTRB1)
Bridge Control (BCTRL)
Capabilities List (CLIST)
PCI Express Capabilities (XCAP)
Device Capabilities (DCAP)
Device Control (DCTL)
Device Status (DSTS)
Link Capabilities (LCAP)
Link Control (LCTL)
Link Status (LSTS)
Slot Capabilities (SLCAP)
Slot Control (SLCTL)
Slot Status (SLSTS)
Root Control (RCTL)
Root Capabilities (ROOTCAP)
Root Status (RSTS)
Device Capabilities 2 (DCAP2)
Device Control 2 (DCTL2)
Device Status 2 (DSTS2)
Link Capabilities 2 (LCAP2)
Link Control 2 (LCTL2)
Link Status 2 (LSTS2)
Slot Capabilities 2 (SLCAP2)
Slot Control 2 (SLCTL2)
Slot Status 2 (SLSTS2)
Message Signaled Interrupt Identifiers (MID)
Message Signaled Interrupt Message (MC)
Message Signaled Interrupt Message Address (MA)
Message Signaled Interrupt Message Upper Address (MUA)
Message Signaled Interrupt Message Data (MD)
Subsystem Vendor Capability (SVCAP)
Subsystem Vendor IDs (SVID)
Power Management Capability (PMCAP)
PCI Power Management Capabilities (PMC)
PCI Power Management Control (PMCS)
Advanced Error Extended (AECH)
Uncorrectable Error Status (UES)
Uncorrectable Error Mask (UEM)
Uncorrectable Error Severity (UEV)
Correctable Error Status (CES)
Correctable Error Mask (CEM)
Advanced Error Capabilities And Control (AECC)
Header Log (HL_DW1)
Header Log (HL_DW2)
Header Log (HL_DW3)
Header Log (HL_DW4)
Root Error Command (REC)
Root Error Status (RES)
Error Source Identification (ESID)
TLP Prefix Log 1 (TLPPL1)
TLP Prefix Log 2 (TLPPL2)
TLP Prefix Log 3 (TLPPL3)
TLP Prefix Log 4 (TLPPL4)
PTM Extended Capability Header (PTMECH)
PTM Capability Register (PTMCAPR)
PTM Control Register (PTMCTLR)
L1 Sub-States Extended Capability Header (L1SECH)
L1 Sub-States Capabilities (L1SCAP)
L1 Sub-States Control 1 (L1SCTL1)
L1 Sub-States Control 2 (L1SCTL2)
L1 Sub-States Status (L1SSTS)
ACS Extended Capability Header (ACSECH)
ACS Capability Register (ACSCAPR)
ACS Control Register (ACSCTLR)
Port VC Capability Register 1 (PVCCR1)
Port VC Capability 2 (PVCC2)
Port VC Control (PVCC)
Port VC Status (PVCS)
Virtual Channel 0 Resource Capability (V0VCRC)
Virtual Channel 0 Resource Control (V0CTL)
Virtual Channel 0 Resource Status (V0STS)
Virtual Channel 1 Resource Capability (V1VCRC)
Virtual Channel 1 Resource Control (V1CTL)
Virtual Channel 1 Resource Status (V1STS)
DPC Extended Capability Header (DPCECH)
DPC Capability Register (DPCCAPR)
DPC Control Register (DPCCTLR)
DPC Status Register (DPCSR)
DPC Error Source ID Register (DPCESIDR)
RP PIO Status Register (RPPIOSR)
RP PIO Mask Register (RPPIOMR)
RP PIO Severity Register (RPPIOVR)
RP PIO SysError Register (RPPIOSER)
RP PIO Exception Register (RPPIOER)
RP PIO Header Log DW1 Register (RPPIOHLR_DW1)
RP PIO Header Log DW2 Register (RPPIOHLR_DW2)
RP PIO Header Log DW3 Register (RPPIOHLR_DW3)
RP PIO Header Log DW4 Register (RPPIOHLR_DW4)
Secondary PCI Express Extended Capability Header (SPEECH)
Link Control 3 (LCTL3)
Lane Error Status (LES)
Lane 0 And Lane 1 Equalization Control (L01EC)
Lane 2 And Lane 3 Equalization Control (L23EC)
Lane 4 And Lane 5 Equalization Control (L45EC)
Lane 6 And Lane 7 Equalization Control (L67EC)
Lane 8 And Lane 9 Equalization Control (L89EC)
Lane 10 And Lane 11 Equalization Control (L1011EC)
Lane 12 And Lane 13 Equalization Control (L1213EC)
Lane 14 And Lane 15 Equalization Control (L1415EC)
Data Link Feature Extended Capability Header (DLFECH)
Data Link Feature Capabilities Register (DLFCAP)
Data Link Feature Status Register (DLFSTS)
Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH)
Physical Layer 16.0 GT/s Capability Register (PL16CAP)
Physical Layer 16.0 GT/s Control Register (PL16CTL)
Physical Layer 16.0 GT/s Status Register (PL16S)
Physical Layer 16.0 GT/s Local Data Parity Mismatch Status Register (PL16LDPMS)
Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS)
Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS)
Physical Layer 16.0 GT/s Extra Status Register (PL16ES)
Physical Layer 16.0 GT/s Lane 01 Equalization Control Register (PL16L01EC)
Physical Layer 16.0 GT/s Lane 23 Equalization Control Register (PL16L23EC)
Physical Layer 16.0 GT/s Lane 45 Equalization Control Register (PL16L45EC)
Physical Layer 16.0 GT/s Lane 67 Equalization Control Register (PL16L67EC)
Physical Layer 16.0 GT/s Lane 89 Equalization Control Register (PL16L89EC)
Physical Layer 16.0 GT/s Lane 1011 Equalization Control Register (PL16L1011EC)
Physical Layer 16.0 GT/s Lane 1213 Equalization Control Register (PL16L1213EC)
Physical Layer 16.0 GT/s Lane 1415 Equalization Control Register (PL16L1415EC)
Physical Layer 32.0 GT/s Extended Capability Header (G5ECH)
Physical Layer 32.0 GT/s Capability Register (G5CAP)
Physical Layer 32.0 GT/s Control Register (G5CTL)
Physical Layer 32.0 GT/s Status Register (G5STS)
Receiver Modified TS Data 1 Register (RCVDMODTSDATA1)
Receiver Modified TS Data 2 Register (RCVDMODTSDATA2)
Transmitted Modified TS Data 1 Register (TRNSMODTSDATA1)
Transmitted Modified TS Data 2 Register (TRNSMODTSDATA2)
32.0 GT/s Lane 0123 Equalization Control Register (G5LANEEQCTL_0)
32.0 GT/s Lane 4567 Equalization Control Register (G5LANEEQCTL_4)
32.0 GT/s Lane 891011 Equalization Control Register (G5LANEEQCTL_8)
32.0 GT/s Lane 12131415 Equalization Control Register (G5LANEEQCTL_12)
Alternate Protocol Extended Capability Header (APEC)
Alternate Protocol Capabilities Register (APCAPR)
Alternate Protocol Control Register (APCTRLR)
Alternate Protocol Data 1 Register (APD1R)
Alternate Protocol Data 2 Register (APD2R)
Alternate Protocol Selective Enable Mask Register (APSEMR)
Multicast Extended Capability Header (MCECH)
Multicast Extended Capability Register (MCAPR)
Multicast Control Register (MCCTLR)
Multicast Base Address Register 1 (MCBADRR1)
Multicast Base Address Register 2 (MCBADRR2)
Multicast Receive Register (MCRR)
Multicast Block All Register (MCBAR)
Multicast Block Untranslated Register (MCBUR)
Multicast Overlay BAR 1 (MCOB1)
Multicast Overlay BAR 2 (MCOB2)
VNN Removal Control (VNNREMCTL)
VNN Removal Save And Restore Hardware Contexts 1 (VNNRSNRC1)
Physical Layer 16.0 GT/s Margining Extended Capability Header (PL16MECH)
Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status Byte 0 & 1 (PL16MPCPSB01)
Physical Layer 16.0 GT/s Margining Port Capabilities and Port Status Byte 2 & 3 (PL16MPCPSB23)
Physical Layer 16.0 GT/s Lane0 Margin Control and Status Register (PL16L0MCS)
Physical Layer 16.0 GT/s Lane1 Margin Control and Status Register (PL16L1MCS)
Physical Layer 16.0 GT/s Lane2 Margin Control and Status Register (PL16L2MCS)
Physical Layer 16.0 GT/s Lane3 Margin Control and Status Register (PL16L3MCS)
Physical Layer 16.0 GT/s Lane4 Margin Control and Status Register (PL16L4MCS)
Physical Layer 16.0 GT/s Lane5 Margin Control and Status Register (PL16L5MCS)
Physical Layer 16.0 GT/s Lane6 Margin Control and Status Register (PL16L6MCS)
Physical Layer 16.0 GT/s Lane7 Margin Control and Status Register (PL16L7MCS)
Physical Layer 16.0 GT/s Lane8 Margin Control and Status Register (PL16L8MCS)
Physical Layer 16.0 GT/s Lane9 Margin Control and Status Register (PL16L9MCS)
Physical Layer 16.0 GT/s Lane10 Margin Control and Status Register (PL16L10MCS)
Physical Layer 16.0 GT/s Lane11 Margin Control and Status Register (PL16L11MCS)
Physical Layer 16.0 GT/s Lane12 Margin Control and Status Register (PL16L12MCS)
Physical Layer 16.0 GT/s Lane13 Margin Control and Status Register (PL16L13MCS)
Physical Layer 16.0 GT/s Lane14 Margin Control and Status Register (PL16L14MCS)
Physical Layer 16.0 GT/s Lane15 Margin Control and Status Register (PL16L15MCS)
PMC I/O Based
Power Management 1 Enables and Status (PM1_EN_STS)
Power Management 1 Control (PM1_CNT)
Power Management 1 Timer (PM1_TMR)
General Purpose Event 1 Status [31:0] (GPE1_STS_31_0)
General Purpose Event 1 Status [63:32] (GPE1_STS_63_32)
General Purpose Event 1 Status [63:32] (GPE1_STS_95_64)
General Purpose Event 1 Enable [31:0] (GPE1_EN_31_0)
General Purpose Event 1 Enable [63:32] (GPE1_EN_63_32)
General Purpose Event 1 Enable [63:32] (GPE1_EN_95_64)
SMI Control and Enable (SMI_EN)
SMI Status Register (SMI_STS)
General Purpose Event Control (GPE_CTRL)
Device Activity Status Register (DEVTRAP_STS)
Therm Timer Delay Register (THERM_TIMER_DELAY)
PM2a Control Block (PM2A_CNT_BLK)
Over-Clocking WDT Control (OC_WDT_CTL)
General Purpose Event 0 Status [31:0] (GPE0_STS_31_0)
General Purpose Event 0 Status [63:32] (GPE0_STS_63_32)
General Purpose Event 0 Status [95:64] (GPE0_STS_95_64)
General Purpose Event 0 Status [127:96] (GPE0_STS_127_96)
General Purpose Event 0 Enable [31:0] (GPE0_EN_31_0)
General Purpose Event 0 Enable [63:32] (GPE0_EN_63_32)
General Purpose Event 0 Enable [95:64] (GPE0_EN_95_64)
General Purpose Event 0 Enable [127:96] (GPE0_EN_127_96)
PMC MMIO
General PM Configuration A (GEN_PMCON_A)
General PM Configuration B (GEN_PMCON_B)
Configured Revision ID (CRID)
Extended Test Mode Register 3 (ETR3)
SET STRAP MSG LOCK (SSML)
SET STRAP MSG CONTROL (SSMC)
SET STRAP MSG DATA (SSMD)
Configured Revision ID (CRID_UIP)
SLP S0 DEBUG REG0 (SLP_S0_DBG_0)
SLP S0 DEBUG REG1 (SLP_S0_DBG_1)
SLP S0 DEBUG REG2 (SLP_S0_DBG_2)
HSIO Power Management Configuration Reg 1 (MODPHY_PM_CFG1)
HSIO Power Management Configuration Reg 2 (MODPHY_PM_CFG2)
HSIO Power Management Configuration Reg 3 (MODPHY_PM_CFG3)
HSIO Power Management Configuration Reg 4 (MODPHY_PM_CFG4)
HSIO Power Management Configuration Reg 5 (MODPHY_PM_CFG5)
HSIO Power Management Configuration Reg 6 (MODPHY_PM_CFG6)
EXT FET RAMP CFG (EXT_FET_RAMP_CFG)
VCCIN AUX CONFIG Register (VCCIN_AUX_CFG)
Always Running Timer Value 31:0 (ARTV_31_0)
Always Running Timer Value 31:0 (ARTV_63_32)
Always Running Timer Value Control (ARTV_CTRL)
Timed GPIO Control 0 (TGPIOCTL0)
Timed GPIO 0 Comparator Value 31:0 (TGPIOCOMPV0_31_0)
Timed GPIO Comparator Value 63:32 (TGPIOCOMPV0_63_32)
Timed GPIO0 Periodic Interval Value 31_0 (TGPIOPIV0_31_0)
Timed GPIO 0 Periodic Interval Value 63_32 (TGPIOPIV0_63_32)
Timed GPIO Time Capture Register 31_0 (TGPIOTCV0_31_0)
Timed GPIO0 Time Capture Register 63_32 (TGPIOTCV0_63_32)
Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV0_31_0)
Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV0_63_32)
Timed GPIO0 Event Counter Register 31_0 (TGPIOEC0_31_0)
Timed GPIO0 Event Counter Register 63_32 (TGPIOEC0_63_32)
Timed GPIO Control 1 (TGPIOCTL1)
Timed GPIO 1 Comparator Value 31:0 (TGPIOCOMPV1_31_0)
Timed GPIO Comparator Value 63:32 (TGPIOCOMPV1_63_32)
Timed GPIO1 Periodic Interval Value 31_0 (TGPIOPIV1_31_0)
Timed GPIO 1 Periodic Interval Value 63_32 (TGPIOPIV1_63_32)
Timed GPIO Time Capture Register 31_0 (TGPIOTCV1_31_0)
Timed GPIO Time Capture Register 63_32 (TGPIOTCV1_63_32)
Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV1_31_0)
Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV1_63_32)
Timed GPIO1 Event Counter Register 31_0 (TGPIOEC1_31_0)
Timed GPIO Event Counter Register 63_32 (TGPIOEC1_63_32)
Min Temperature (MIN_TEMP)
Max Temperature (MAX_TEMP)
Catastrophic Trip Point Enable (CTEN)
Throttle Level (TL)
Throttle Levels Enable (TLEN)
Thermal Sensor Alert High Value (TSAHV)
Thermal Sensor Alert Low Value (TSALV)
Thermal Alert Trip Status (TAS)
Processor Hot Level Control (PHLC)
Temperature Sensor Control and Status (TSS0)
SoC-to-IOE Force Thermal Throttling Control (S2I_FTT_CTRL)
SoC Internal Fabric Thermal Throttling Configuration (SOCIFTTC)
Low Power Mode Enable (LPM_EN)
Wake Alarm Device Timer: AC (WADT_AC)
Wake Alarm Device Timer: DC (WADT_DC)
Wake Alarm Device Expired Timer: AC (WADT_EXP_AC)
Wake Alarm Device Expired Timer: DC (WADT_EXP_DC)
Power and Reset Status (PRSTS)
Power Management Configuration Reg 1 (PM_CFG)
S3 Power Gating Policies (S3_PWRGATE_POL)
S4 Power Gating Policies (S4_PWRGATE_POL)
S5 Power Gating Policies (S5_PWRGATE_POL)
DeepSx Configuration (DSX_CFG)
Power Management Configuration Reg 2 (PM_CFG2)
Chipset Initialization Register 18E0 (PM_CFG3)
Compute Tile Early Power-on Configuration (CPU_EPOC)
ACPI Timer Control (ACPI_TMR_CTL)
Last TSC Alarm Value[31:0] (TSC_ALARM_LO)
Last TSC Alarm Value[63:32] (TSC_ALARM_HI)
GPIO Configuration (GPIO_CFG)
Global Reset Causes 0 (GBLRST_CAUSE0)
Global Reset Causes 1 (GBLRST_CAUSE1)
Host Partition Reset Causes (HPR_CAUSE0)
Latency Limit Residency 0 (LAT_LIM_RES_0)
Latency Limit Residency 1 (LAT_LIM_RES_1)
Latency Limit Residency 2 (LAT_LIM_RES_2)
SLP_S0 Residency (SLP_S0_RESIDENCY)
Latency Limit Control (LATENCY_LIMIT_CONTROL)
ACPI Control (ACTL)
S0 Residency (S0_RES)
PGD PG_ACK Status Register 1 (PPASR2)
PGD PFET Enable Ack Status Register 0 (PPFEAR0)
PGD PFET Enable Ack Status Register 1 (PPFEAR1)
PGD PFET Enable Ack Status Register 1 (PPFEAR2)
PGD Ungate Latency Specification Register 1 (PUGLSR1)
PGD PG_REQ Status Register 0 (PPRSR0)
PGD PG_REQ Status Register 1 (PPRSR1)
PGD PG_REQ Status Register 1 (PPRSR2)
ST_PG_FDIS_PMC - Register 1 (ST_PG_FDIS_PMC_1)
ST_PG_FDIS_PMC - Register 2 (ST_PG_FDIS_PMC_2)
LPM IPD3_THC1 BLK CNTR (LPM_IPD3_THC1_BLK_CNTR)
PMC PCI Configuration (D31:F2)
Device Vendor ID (DEVVENDID)
Status and Command (STATUSCOMMAND)
Revision Class Codes (REVCLASSCODE)
Cache Line Latency Header And BIST (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register 1 (BAR1)
Base Address Register 1 High (BAR1_HIGH)
Base Address Register2 (BAR2)
Subsystem Identifiers (SUBSYSTEMID)
EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
PowerManagement Capability ID (POWERCAPID)
Power Management Control and Status (PMECTRLSTATUS)
PCI Device Idle Capability Record (PCIDEVIDLE_CAP_RECORD)
Device Vendor Specific (DEVID_VEND_SPECIFIC_REG)
D0I3 CONTROL SW LTR MMIO REG (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device IDLE pointer register (DEVICE_IDLE_POINTER_REG)
D0I3 MAX POW LAT PG CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write Register1 (GEN_REGRW1)
General Purpose Read Write Register2 (GEN_REGRW2)
General Purpose Read Write Register3 (GEN_REGRW3)
General Purpose Read Write Register4 (GEN_REGRW4)
General Purpose Input Register (GEN_INPUT_REG)
RTC I/O
Seconds Value (Sec)
Seconds Alarm (Sec_Alarm)
Minutes Value (Minutes)
Minutes Alarm (Minutes_Alarm)
Hours Value (Hours)
Hours Alarm (Hours_Alarm)
Day Of Week (Day_of_Week)
Day Of Month (Day_of_Month)
Month Value (Month)
Year Value (Year)
Register A (Register_A)
Register B General Configuration (Register_B)
Register C Flag Register (Register_C)
Register D Flag Register (Register_D)
114 Bytes Of Lower User RAM (Register_E)
128 Bytes Of Upper User RAM (Register_80)
Shared SRAM PCI Configuration (D20:F2)
Device Vendor ID (DEVVENDID)
STATUSCOMMAND Status and Command (STATUSCOMMAND)
Revision Class Codes (REVCLASSCODE)
CLLATHEADERBIST Cache Line Latency Header And BIST (CLLATHEADERBIST)
32-bit Base Address Register (BAR)
BAR HIGH (BAR_HIGH)
32-bit Base Address Register1 (BAR1)
BAR1 HIGH (BAR1_HIGH)
Subsystem Identifiers (SUBSYSTEMID)
EXPANSION ROM BASEADDR (EXPANSION_ROM_BASEADDR)
CAPABILITY PTR (CAPABILITYPTR)
INTERRUPT REG Interrupt Register (INTERRUPTREG)
POWER CAP ID PowerManagement Capability ID (POWERCAPID)
PME CTRL STATUS (PMECTRLSTATUS)
PCIDEVIDLE CAP RECORD (PCIDEVIDLE_CAP_RECORD)
DEVID VEND SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)
D0I3 CONTROL SW LTR MMIO REG (D0I3_CONTROL_SW_LTR_MMIO_REG)
DEVICE IDLE POINTER REG (DEVICE_IDLE_POINTER_REG)
D0I3 MAX POW LAT PG CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG)
GEN REG RW1 (GEN_REGRW1)
GEN REG RW2 (GEN_REGRW2)
GEN REG RW3 (GEN_REGRW3)
GEN REG RW4 (GEN_REGRW4)
GEN INPUT REG (GEN_INPUT_REG)
SMBus TCO I/O
TCO_RLD Register (TRLD)
TCO_DAT_IN Register (TDI)
TCO_DAT_OUT Register (TDO)
TCO1_STS Register (TSTS1)
TCO2_STS Register (TSTS2)
TCO1_CNT Register (TCTL1)
TCO2_CNT Register (TCTL2)
TCO Message Registers (TMSG)
TCO_WDSTATUS Register (TWDS)
Reserved_1 Register (RSV_1)
LEGACY_ELIM Register (LE)
Reserved_2 Register (RSV_2)
TCO_TMR Register (TTMR)
Reserved Register (RSV_3)
Reserved Register (RSV_4)
Reserved Register (RSV_5)
SPI MMIO
BIOS Flash Primary Region (BIOS_BFPREG)
Hardware Sequencing Flash Status and Control (BIOS_HSFSTS_CTL)
Flash Address (BIOS_FADDR)
Discrete Lock Bits (BIOS_DLOCK)
Flash Data (BIOS_FDATA0)
Flash Data (BIOS_FDATA1)
Flash Data (BIOS_FDATA2)
Flash Data (BIOS_FDATA3)
Flash Data (BIOS_FDATA4)
Flash Data (BIOS_FDATA5)
Flash Data (BIOS_FDATA6)
Flash Data (BIOS_FDATA7)
Flash Data (BIOS_FDATA8)
Flash Data (BIOS_FDATA9)
Flash Data (BIOS_FDATA10)
Flash Data (BIOS_FDATA11)
Flash Data (BIOS_FDATA12)
Flash Data (BIOS_FDATA13)
Flash Data (BIOS_FDATA14)
Flash Data (BIOS_FDATA15)
Flash Region Access Permissions (BIOS_FRACC)
Flash Region (BIOS_FREG0)
Flash Region (BIOS_FREG1)
Flash Region (BIOS_FREG2)
Flash Region (BIOS_FREG3)
Flash Region (BIOS_FREG4)
Flash Region (BIOS_FREG5)
Flash Region (BIOS_FREG6)
Flash Region (BIOS_FREG7)
Flash Region (BIOS_FREG8)
Flash Region (BIOS_FREG9)
Flash Region (BIOS_FREG10)
Flash Region (BIOS_FREG11)
Flash Protected Range (BIOS_FPR0)
Flash Protected Range (BIOS_FPR1)
Flash Protected Range (BIOS_FPR2)
Flash Protected Range (BIOS_FPR3)
Flash Protected Range (BIOS_FPR4)
Global Protected Range 0 (BIOS_GPR0)
Secondary Flash Region Access Permissions (BIOS_SFRACC)
Flash Descriptor Observability Control (BIOS_FDOC)
Flash Descriptor Observability Data (BIOS_FDOD)
Additional Flash Control (BIOS_AFC)
Vendor Specific Component Capabilities for Component 0 (BIOS_SFDP0_VSCC0)
Vendor Specific Component Capabilities for Component 1 (BIOS_SFDP1_VSCC1)
Parameter Table Index (BIOS_PTINX)
Parameter Table Data (BIOS_PTDATA)
SPI Bus Requester Status (BIOS_SBRS)
Flash Region (BIOS_FREG12)
Flash Region (BIOS_FREG13)
Flash Region (BIOS_FREG14)
Flash Region (BIOS_FREG15)
RPMC SFDP Table (BIOS_RPMC0_D0)
RPMC SFDP Table (BIOS_RPMC1_D0)
RPMC SFDP Table (BIOS_RPMC0_D1)
RPMC SFDP Table (BIOS_RPMC1_D1)
BIOS Master Read Access Permissions (BIOS_BM_RAP)
BIOS Master Write Access Permissions (BIOS_BM_WAP)
SPI PCI Configuration (D31:F5)
Device ID and Vendor ID (BIOS_SPI_DID_VID)
Status and Command (BIOS_SPI_STS_CMD)
Revision ID and Class Code (BIOS_SPI_CC_RID)
BIST, Header Type, Latency Timer, Cache Line Size (BIOS_SPI_BIST_HTYPE_LT_CLS)
SPI BAR0 MMIO (BIOS_SPI_BAR0)
Subsystem and Vendor ID (BIOS_SPI_SID_SVID)
BIOS Direct Read DMA Base Address High (BIOS_RD_DMA_BA_HI)
BIOS Direct Read DMA Base Address (BIOS_RD_DMA_BA)
BIOS Direct Read DMA Base Offset (BIOS_RD_DMA_BASE_OFFSET)
BIOS Direct Read DMA Status (BIOS_RD_DMA_STS)
SPI Unsupported Request Status (BIOS_SPI_UR_STS_CTL)
BIOS Decode Enable (BIOS_SPI_BDE)
BIOS Control (BIOS_SPI_BC)
SPI BAR1 MMIO (BIOS_SPI_BAR1)
TCSS IOM MAIN
IOM CSME IMR MG STATUS REG (IOM_CSME_IMR_MG_STATUS)
Thunderbolt Firmware Status in IMR (IOM_CSME_IMR_TBT_STATUS)
IOM TBT STATUS (IOM_TBT_STATUS_0)
IOM TBT STATUS (IOM_TBT_STATUS_1)
IOM TBT STATUS (IOM_TBT_STATUS_2)
IOM AUX ORI BIAS CTRL (IOM_AUX_ORI_BIAS_CTRL_PUP[0])
IOM AUX ORI BIAS CTRL (IOM_AUX_ORI_BIAS_CTRL_PUP[1])
IOM AUX ORI BIAS CTRL (IOM_AUX_ORI_BIAS_CTRL_PUP[2])
IOM AUX ORI BIAS CTRL (IOM_AUX_ORI_BIAS_CTRL_PDN[0])
IOM AUX ORI BIAS CTRL (IOM_AUX_ORI_BIAS_CTRL_PDN[1])
IOM AUX ORI BIAS CTRL (IOM_AUX_ORI_BIAS_CTRL_PDN[2])
IP PM CONFIGURATION REGISTER (PCIE_PM_CONFIG[0])
IP PM CONFIGURATION REGISTER (PCIE_PM_CONFIG[1])
IP PM CONFIGURATION REGISTER (PCIE_PM_CONFIG[2])
IP PM CONFIGURATION REGISTER (FIA_PM_CONFIG[0])
IP PM CONFIGURATION REGISTER (FIA_PM_CONFIG[1])
IP PM CONFIGURATION REGISTER (TBT_PM_CONFIG[0])
IP PM CONFIGURATION REGISTER (TBT_PM_CONFIG[1])
IOM FW CURRENT STATUS REG (IOM_FW_CURRENT_STATUS)
IOM FW CURRENT TASK REG (IOM_FW_CURRENT_TASK)
IOM FW INFO (IOM_FW_INFO)
IOM FW INFO ENGR (IOM_FW_INFO_ENGR)
IP PM CONFIGURATION REGISTER (IOM_PM_CONFIG)
IOM PM STATUS REG (IOM_PM_STATUS)
IP PM CONFIGURATION REGISTER (USB_XDCI_PM_CONFIG)
IP PM CONFIGURATION REGISTER (USB_XHCI_PM_CONFIG)
IOM AUX ORI BIAS CTRL (IOM_AUX_ISO_CTRL[0])
IOM AUX ORI BIAS CTRL (IOM_AUX_ISO_CTRL[1])
IOM AUX ORI BIAS CTRL (IOM_AUX_ISO_CTRL[2])
TCSS xHCI PCI Configuration (D13:F0)
Device Id And Vendor Id Register (DEVVENDID)
Status And Command (STATUSCOMMAND)
Revision Id And Class Code (REVCLASSCODE)
Cache Line Latency Header And Bist (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Subsystem Vendor And Subsystem Id (SUBSYSTEMID)
Expansion Rom Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer Register (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Capability Id (POWERCAPID)
Power Management Control And Status Register (PMECTRLSTATUS)
Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD)
Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG)
Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG)
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)
Touch Host Controller (THC) MMIO Port
THC SPI Bus Configuration Register (THC_M_PRT_SPI_CFG)
THC SPI Bus Read Opcode Register (THC_M_PRT_SPI_DMARD_OPCODE)
THC Interrupt Enable Register (THC_M_PRT_INT_EN)
THC Interrupt Status Register (THC_M_PRT_INT_STATUS)
THC Error Cause Register (THC_M_PRT_ERR_CAUSE)
THC SW sequencing Control (THC_M_PRT_SW_SEQ_CNTRL)
THC SW sequencing Status (THC_M_PRT_SW_SEQ_STS)
THC SW Sequencing Data DW0 or SPI Address Register (THC_M_PRT_SW_SEQ_DATA0_ADDR)
THC SW sequencing Data DW1 (THC_M_PRT_SW_SEQ_DATA1)
THC SW sequencing Data DW2 (THC_M_PRT_SW_SEQ_DATA2)
THC SW sequencing Data DW3 (THC_M_PRT_SW_SEQ_DATA3)
THC SW sequencing Data DW4 (THC_M_PRT_SW_SEQ_DATA4)
THC SW sequencing Data DW5 (THC_M_PRT_SW_SEQ_DATA5)
THC SW sequencing Data DW6 (THC_M_PRT_SW_SEQ_DATA6)
THC SW sequencing Data DW7 (THC_M_PRT_SW_SEQ_DATA7)
THC SW sequencing Data DW8 (THC_M_PRT_SW_SEQ_DATA8)
THC SW sequencing Data DW9 (THC_M_PRT_SW_SEQ_DATA9)
THC SW sequencing Data DW10 (THC_M_PRT_SW_SEQ_DATA10)
THC SW sequencing Data DW11 (THC_M_PRT_SW_SEQ_DATA11)
THC SW sequencing Data DW12 (THC_M_PRT_SW_SEQ_DATA12)
THC SW sequencing Data DW13 (THC_M_PRT_SW_SEQ_DATA13)
THC SW sequencing Data DW14 (THC_M_PRT_SW_SEQ_DATA14)
THC SW sequencing Data DW15 (THC_M_PRT_SW_SEQ_DATA15)
THC SW sequencing Data DW16 (THC_M_PRT_SW_SEQ_DATA16)
THC Write PRD Base Address Register Low (THC_M_PRT_WPRD_BA_LOW)
THC Write PRD Base Address Register High (THC_M_PRT_WPRD_BA_HI)
THC Write DMA Control (THC_M_PRT_WRITE_DMA_CNTRL)
THC Write Interrupt Status (THC_M_PRT_WRITE_INT_STS)
THC device address for the bulk write (THC_M_PRT_WR_BULK_ADDR)
THC Device Interrupt Cause Register Address (THC_M_PRT_DEV_INT_CAUSE_ADDR)
THC Device Interrupt Cause Register Value (THC_M_PRT_DEV_INT_CAUSE_REG_VAL)
THC TXDMA Frame Count (THC_M_PRT_TX_FRM_CNT)
THC TXDMA Packet Count (THC_M_PRT_TXDMA_PKT_CNT)
THC Device Interrupt Count on this port (THC_M_PRT_DEVINT_CNT)
Touch Device Interrupt Cause register Format Configuration Register 1 (THC_M_PRT_DEVINT_CFG_1)
Touch Device Interrupt Cause register Format Configuration Register 2 (THC_M_PRT_DEVINT_CFG_2)
THC Read PRD Base Address Low for the 1st RXDMA (THC_M_PRT_RPRD_BA_LOW_1)
THC Read PRD Base Address High for the 1st RXDMA (THC_M_PRT_RPRD_BA_HI_1)
THC Read PRD Control for the 1st RXDMA (THC_M_PRT_RPRD_CNTRL_1)
THC Read DMA Control for the 1st RXDMA (THC_M_PRT_READ_DMA_CNTRL_1)
THC Read Interrupt Status for the 1st RXDMA (THC_M_PRT_READ_DMA_INT_STS_1)
THC Read DMA Error Register for the 1st RXDMA (THC_M_PRT_READ_DMA_ERR_1)
Touch Sequencer GuC Tail Offset Address Low for the 1st RXDMA (THC_M_PRT_GUC_OFFSET_LOW_1)
Touch Sequencer GuC Tail Offset Address High for the 1st RXDMA (THC_M_PRT_GUC_OFFSET_HI_1)
Touch Host Controller GuC Work Queue Item Size for the 1st RXDMA (THC_M_PRT_GUC_WORKQ_ITEM_SZ_1)
Touch Host Controller GuC Control register for the 1st RXDMA (THC_M_PRT_GUC_WORKQ_SZ_1)
Touch Sequencer Control for the 1st DMA (THC_M_PRT_TSEQ_CNTRL_1)
Touch Sequencer GuC Doorbell Address Low for the 1st RXDMA (THC_M_PRT_GUC_DB_ADDR_LOW_1)
Touch Sequencer GuC Doorbell Address High for the 1st RXDMA (THC_M_PRT_GUC_DB_ADDR_HI_1)
Touch Sequencer GuC Doorbell Data (THC_M_PRT_GUC_DB_DATA_1)
Touch Sequencer GuC Tail Offset Initial Value for the 1st RXDMA (THC_M_PRT_GUC_OFFSET_INITVAL_1)
THC Device Address for the bulk/touch data read for the 1st RXDMA (THC_M_PRT_RD_BULK_ADDR_1)
THC Gfx/SW Doorbell Count from the 1st Stream RXDMA on this port (THC_M_PRT_DB_CNT_1)
THC Frame Count from the 1st Stream RXDMA on this port (THC_M_PRT_FRM_CNT_1)
THC Micro Frame Count from the 1st Stream RXDMA on this port (THC_M_PRT_UFRM_CNT_1)
THC Packet Count from the 1st Stream RXDMA on this port (THC_M_PRT_RXDMA_PKT_CNT_1)
THC Software Interrupt Count from the 1st Stream RXDMA on this port (THC_M_PRT_SWINT_CNT_1)
Touch Sequencer Frame Drop Counter for the 1st RXDMA (THC_M_PRT_FRAME_DROP_CNT_1)
THC Coaescing 1 (THC_M_PRT_COALESCE_1)
THC Read PRD Base Address Low for the 2nd RXDMA (THC_M_PRT_RPRD_BA_LOW_2)
THC Read PRD Base Address High for the 2nd RXDMA (THC_M_PRT_RPRD_BA_HI_2)
THC Read PRD Control for the 2nd RXDMA (THC_M_PRT_RPRD_CNTRL_2)
THC Read DMA Control for the 2nd RXDMA (THC_M_PRT_READ_DMA_CNTRL_2)
THC Read Interrupt Status for the 2nd RXDMA (THC_M_PRT_READ_DMA_INT_STS_2)
THC Read DMA Error Register for the 2nd RXDMA (THC_M_PRT_READ_DMA_ERR_2)
Touch Sequencer GuC Tail Offset Address Low for the 2nd RXDMA (THC_M_PRT_GUC_OFFSET_LOW_2)
Touch Sequencer GuC Tail Offset Address High for the 2nd RXDMA (THC_M_PRT_GUC_OFFSET_HI_2)
Touch Host Controller GuC Work Queue Item Size for the 2nd RXDMA (THC_M_PRT_GUC_WORKQ_ITEM_SZ_2)
Touch Host Controller GuC Control register for the 2nd RXDMA (THC_M_PRT_GUC_WORKQ_SZ_2)
Touch Sequencer Control for the 2nd DMA (THC_M_PRT_TSEQ_CNTRL_2)
Touch Sequencer GuC Doorbell Address Low for the 2nd RXDMA (THC_M_PRT_GUC_DB_ADDR_LOW_2)
Touch Sequencer GuC Doorbell Address High for the 2nd RXDMA (THC_M_PRT_GUC_DB_ADDR_HI_2)
Touch Sequencer GuC Doorbell Data for PRD2 (THC_M_PRT_GUC_DB_DATA_2)
Touch Sequencer GuC Tail Offset Initial Value for the 2nd RXDMA (THC_M_PRT_GUC_OFFSET_INITVAL_2)
THC Device Address for the bulk/touch data read for the 2nd RXDMA (THC_M_PRT_RD_BULK_ADDR_2)
THC Gfx/SW Doorbell Count from the 2nd Stream RXDMA on this port (THC_M_PRT_DB_CNT_2)
THC Frame Count from the 2nd Stream RXDMA on this port (THC_M_PRT_FRM_CNT_2)
THC Micro Frame Count from the 2nd Stream RXDMA on this port (THC_M_PRT_UFRM_CNT_2)
THC Packet Count from the 2nd Stream RXDMA on this port (THC_M_PRT_RXDMA_PKT_CNT_2)
THC Software Interrupt Count from the 2nd Stream RXDMA on this port (THC_M_PRT_SWINT_CNT_2)
Touch Sequencer Frame Drop Counter for the 2nd RXDMA (THC_M_PRT_FRAME_DROP_CNT_2)
THC Read PRD Base Address High for the SW RXDMA (THC_M_PRT_RPRD_BA_HI_SW)
THC timing based Frame/Interrupt caolescing control register for 1st RXDMA (THC_M_PRT_COALESCE_CNTRL_1)
THC timing based Frame/Interrupt caolescing control register for 2nd RXDMA (THC_M_PRT_COALESCE_CNTRL_2)
Touch Host Controller (THC) PCI Configuration (D16:F0/1)
Device ID and Vendor ID (THC_CFG_DID_VID)
Status and Command (THC_CFG_STS_CMD)
Revision ID and Class Code (THC_CFG_CC_RID)
BIST_Header Type_Latency Timer_Cache Line Size (THC_CFG_BIST_HTYPE_LT_CLS)
THC BAR0 MMIO Low (THC_CFG_BAR0_LOW)
THC BAR0 MMIO High (THC_CFG_BAR0_HI)
Subsystem and Vendor ID (THC_CFG_SID_SVID)
Capability List Pointer (THC_CFG_CAPP)
Interrupt Configuration (THC_CFG_INT)
THC Unsupported Request Status (THC_CFG_UR_STS_CTL)
MSI Message Control_ Next Pointer and Capability ID (THC_CFG_MSIMC_MSINP_MSICID)
MSI Message Address (THC_CFG_MSIMA)
MSI Message Upper Address (THC_CFG_MSIMUA)
MSI Message Data (THC_CFG_MSIMD)
PCI Power Management Capability (THC_CFG_PMCAP_PMNP_PMCID)
PCI Power Management Control and Status (THC_CFG_PMD_PMCSRBSE_PMCSR)
Device Idle Capability (THC_CFG_DEVIDLE)
Vendor Specific Header (THC_CFG_VSHDR)
SW LTR Pointer Regsiter (THC_CFG_SWLTRPTR)
Device Idle Pointer Register (THC_CFG_DEVIDLEPTR)
Device Idle Power On Latency (THC_CFG_DEVIDLEPOL)
Power Control Enables (THC_CFG_PCE)
UART Additional MMIO
REG CLOCKS (CLOCKS)
REG RESETS (RESETS)
REG GENERAL (GENERAL)
REG ACTIVELTR_VALUE (ACTIVELTR_VALUE)
REG IDLELTR_VALUE (IDLELTR_VALUE)
REG TX_BYTE_COUNT (TX_BYTE_COUNT)
REG RX_BYTE_COUNT (RX_BYTE_COUNT)
REG Spare_0 (Spare_0)
REG Spare_1 (Spare_1)
REG SW_SCRATCH_0 (SW_SCRATCH_0)
REG SW_SCRATCH_1 (SW_SCRATCH_1)
REG SW_SCRATCH_2 (SW_SCRATCH_2)
REG SW_SCRATCH_3 (SW_SCRATCH_3)
REG CLOCK_GATE (CLOCK_GATE)
REG Reserved1 (Reserved1)
REG REMAP_ADDR_LO (REMAP_ADDR_LO)
REG REMAP_ADDR_HI (REMAP_ADDR_HI)
REG Reserved2 (Reserved2)
REG DEVIDLE_CONTROL (DEVIDLE_CONTROL)
REG CTS_Override (CTS_Override)
REG UART_HVM_MISR_CRCOUT (UART_HVM_MISR_CRCOUT)
REG CAPABLITIES (CAPABLITIES)
UART DMA Controller
REG SAR_LO0 (SAR_LO0)
REG SAR_HI0 (SAR_HI0)
REG DAR_LO0 (DAR_LO0)
REG DAR_HI0 (DAR_HI0)
REG LLP_LO0 (LLP_LO0)
REG LLP_HI0 (LLP_HI0)
REG CTL_LO0 (CTL_LO0)
REG CTL_HI0 (CTL_HI0)
REG SSTAT0 (SSTAT0)
REG DSTAT0 (DSTAT0)
REG SSTATAR_LO0 (SSTATAR_LO0)
REG SSTATAR_HI0 (SSTATAR_HI0)
REG DSTATAR_LO0 (DSTATAR_LO0)
REG DSTATAR_HI0 (DSTATAR_HI0)
REG CFG_LO0 (CFG_LO0)
REG CFG_HI0 (CFG_HI0)
REG SGR0 (SGR0)
REG DSR0 (DSR0)
REG SAR_LO1 (SAR_LO1)
REG SAR_HI1 (SAR_HI1)
REG DAR_LO1 (DAR_LO1)
REG DAR_HI1 (DAR_HI1)
REG LLP_LO1 (LLP_LO1)
REG LLP_HI1 (LLP_HI1)
REG CTL_LO1 (CTL_LO1)
REG CTL_HI1 (CTL_HI1)
REG SSTAT1 (SSTAT1)
REG DSTAT1 (DSTAT1)
REG SSTATAR_LO1 (SSTATAR_LO1)
REG SSTATAR_HI1 (SSTATAR_HI1)
REG DSTATAR_LO1 (DSTATAR_LO1)
REG DSTATAR_HI1 (DSTATAR_HI1)
REG CFG_LO1 (CFG_LO1)
REG CFG_HI1 (CFG_HI1)
REG SGR1 (SGR1)
REG DSR1 (DSR1)
REG RawTfr (RawTfr)
REG RawBlock (RawBlock)
REG RawSrcTran (RawSrcTran)
REG RawDstTran (RawDstTran)
REG RawErr (RawErr)
REG StatusTfr (StatusTfr)
REG StatusBlock (StatusBlock)
REG StatusSrcTran (StatusSrcTran)
REG StatusDstTran (StatusDstTran)
REG StatusErr (StatusErr)
REG MaskTfr (MaskTfr)
REG MaskBlock (MaskBlock)
REG MaskSrcTran (MaskSrcTran)
REG MaskDstTran (MaskDstTran)
REG MaskErr (MaskErr)
REG ClearTfr (ClearTfr)
REG ClearBlock (ClearBlock)
REG ClearSrcTran (ClearSrcTran)
REG ClearDstTran (ClearDstTran)
REG ClearErr (ClearErr)
REG StatusInt (StatusInt)
REG DmaCfgReg (DmaCfgReg)
REG ChEnReg (ChEnReg)
REG Reserved0_CPL (Reserved0_CPL)
REG Reserved0_CPH (Reserved0_CPH)
REG Reserved1_CPL (Reserved1_CPL)
REG Reserved1_CPH (Reserved1_CPH)
REG Reserved0_FPL (Reserved0_FPL)
REG Reserved0_FPH (Reserved0_FPH)
REG Reserved1_FPL (Reserved1_FPL)
REG Reserved1_FPH (Reserved1_FPH)
REG SAI_ERR (SAI_ERR)
REG GLOBAL_CFG (GLOBAL_CFG)
UART MMIO
REG DLL (DLL)
REG THR (THR)
REG RBR (RBR)
REG IER (IER)
REG DLH (DLH)
REG FCR (FCR)
REG IIR (IIR)
REG LCR (LCR)
REG MCR (MCR)
REG LSR (LSR)
REG MSR (MSR)
REG SCR (SCR)
REG SRBR_STHR0 (SRBR_STHR0)
REG SRBR_STHR1 (SRBR_STHR1)
REG SRBR_STHR2 (SRBR_STHR2)
REG SRBR_STHR3 (SRBR_STHR3)
REG SRBR_STHR4 (SRBR_STHR4)
REG SRBR_STHR5 (SRBR_STHR5)
REG SRBR_STHR6 (SRBR_STHR6)
REG SRBR_STHR7 (SRBR_STHR7)
REG SRBR_STHR8 (SRBR_STHR8)
REG SRBR_STHR9 (SRBR_STHR9)
REG SRBR_STHR10 (SRBR_STHR10)
REG SRBR_STHR11 (SRBR_STHR11)
REG SRBR_STHR12 (SRBR_STHR12)
REG SRBR_STHR13 (SRBR_STHR13)
REG SRBR_STHR14 (SRBR_STHR14)
REG SRBR_STHR15 (SRBR_STHR15)
REG FAR (FAR)
REG TFR (TFR)
REG RFW (RFW)
REG USR (USR)
REG TFL (TFL)
REG RFL (RFL)
REG SRR (SRR)
REG SRTS (SRTS)
REG SBCR (SBCR)
REG SDMAM (SDMAM)
REG SFE (SFE)
REG SRT (SRT)
REG STET (STET)
REG HTX (HTX)
REG DMASA (DMASA)
REG CPR (CPR)
REG UCV (UCV)
REG CTR (CTR)
UART PCI Configuration (D30:F0/1, D25:F2)
Device Id And Vendor Id Register (DEVVENDID)
Status And Command (STATUSCOMMAND)
Revision Id And Class Code (REVCLASSCODE)
Cache Line Latency Header And Bist (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Subsystem Vendor And Subsystem Id (SUBSYSTEMID)
Expansion Rom Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer Register (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Control And Status Register (PMECTRLSTATUS)
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)
UFS PCI Configuration (D18:F7)
Device Id And Vendor Id Register (DEVVENDID)
Status And Command (STATUSCOMMAND)
Revision Id And Class Code (REVCLASSCODE)
Cache Line Latency Header And Bist (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Subsystem Vendor And Subsystem Id (SUBSYSTEMID)
Expansion Rom Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer Register (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Capability Id (POWERCAPID)
Power Management Control And Status Register (PMECTRLSTATUS)
Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD)
Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG)
Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG)
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write Register1 (GEN_REGRW1)
General Purpose Read Write Register2 (GEN_REGRW2)
General Purpose Read Write Register3 (GEN_REGRW3)
General Purpose Read Write Register4 (GEN_REGRW4)
General Purpose Input Register (GEN_INPUT_REG)
xHCI MMIO
Capability Registers Length (CAPLENGTH)
Host Controller Interface Version Number (HCIVERSION)
Structural Parameters 1 (HCSPARAMS1)
Structural Parameters 2 (HCSPARAMS2)
Structural Parameters 3 (HCSPARAMS3)
Capability Parameters (HCCPARAMS)
Doorbell Offset (DBOFF)
Runtime Register Space Offset (RTSOFF)
USB Command (USBCMD)
USB Status (USBSTS)
Page Size (PAGESIZE)
Device Notification Control (DNCTRL)
Command Ring Low (CRCR_LO)
Command Ring High (CRCR_HI)
Device Context Base Address Array Pointer Low (DCBAAP_LO)
Device Context Base Address Array Pointer High (DCBAAP_HI)
Configure Reg (CONFIG)
Port Status AndControl USB2 (PORTSC1)
Port Power Management Status and Control USB2 (PORTPMSC1)
Port X Hardware LPM Control Register (PORTHLPMC1)
Port Power Management Status And Control USB3 (PORTPMSC9)
USB3 Port Link Info (PORTLI9)
XECP SUPP USB2_3 (PORTPMSC10)
Microframe Index (RTMFINDEX)
Interrupter Management (IMAN0)
Event Ring Segment Table Size (ERSTSZ0)
Event Ring Segment Table Base Address Low (ERSTBA_LO0)
Event Ring Segment Table Base Address High (ERSTBA_HI0)
Event Ring Dequeue Pointer Low (ERDP_LO0)
Event Ring Dequeue Pointer High (ERDP_HI0)
Door Bell (DB0)
XECP SUPP USB2_1 (XECP_SUPP_USB2_1)
XECP SUPP USB2_2 (XECP_SUPP_USB2_2)
XECP SUPP USB2_3 (XECP_SUPP_USB2_3)
XECP SUPP USB2_4 Full Speed (XECP_SUPP_USB2_4)
XECP_SUPP USB2_5 Low Speed (XECP_SUPP_USB2_5)
XECP SUPP USB2_6 High Speed (XECP_SUPP_USB2_6)
XECP SUPP USB3_0 (XECP_SUPP_USB3_0)
XECP SUPP USB3_1 (XECP_SUPP_USB3_1)
XECP SUPP USB3_2 (XECP_SUPP_USB3_2)
XECP SUPP USB3_3 (XECP_SUPP_USB3_3)
XECP SUPP USB3_4 (XECP_SUPP_USB3_4)
XECP SUPP USB3_5 (XECP_SUPP_USB3_5)
XECP SUPP USB3_6 (XECP_SUPP_USB3_6)
XECP SUPP USB3_7 (XECP_SUPP_USB3_7)
Host Control Scheduler (HOST_CTRL_SCH_REG)
Power Management Control (PMCTRL_REG)
Host Controller Misc Reg (HOST_CTRL_MISC_REG)
Super Speed Port Enable (SSPE_REG)
AUX Power Management Control (AUX_CTRL_REG1)
SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG)
USB2 Port Link Control 1 (USB2_LINK_MGR_CTRL_REG1)
USB2 Port Link Control 2 (USB2_LINK_MGR_CTRL_REG2)
USB2 Port Link Control 3 (USB2_LINK_MGR_CTRL_REG3)
USB2 Port Link Control 4 (USB2_LINK_MGR_CTRL_REG4)
Power Scheduler Control-0 (PWR_SCHED_CTRL0)
Power Scheduler Control-1 (PWR_SCHED_CTRL2)
AUX Power Management Control (AUX_CTRL_REG2)
XHCI Aux Clock Control Register (XHCI_AUX_CCR)
XHC Latency Tolerance Parameters LTV Control (XLTP_LTV1)
XHC Latency Tolerance Parameters LTV Control 2 (XLTP_LTV2)
XHC Latency Tolerance Parameters High Idle Time Control (XLTP_HITC)
XHC Latency Tolerance Parameters Medium Idle Time Control (XLTP_MITC)
XHC Latency Tolerance Parameters Low Idle Time Control (XLTP_LITC)
LFPS On Count (LFPSONCOUNT_REG)
USB2 Power Management Control (USB2PMCTRL_REG)
USB Legacy Support Capability (USBLEGSUP)
USB Legacy Support Control Status (USBLEGCTLSTS)
Port Disable Override Capability Register (PDO_CAPABILITY)
Programming Interface (PI_MMIO)
Sub Class Code (SCC_MMIO)
Serial Bus Release Number (SBRN_MMIO)
Debug Capability ID Register (DCID)
GLOBAL TIME SYNC CAP REG (GLOBAL_TIME_SYNC_CAP_REG)
GLOBAL TIME SYNC CTRL REG (GLOBAL_TIME_SYNC_CTRL_REG)
MICROFRAME TIME REG (MICROFRAME_TIME_REG)
Global Time Value (Low Register) (GLOBAL_TIME_LOW_REG)
Global Time High (GLOBAL_TIME_HI_REG)
XHCI USB2 Overcurrent Pin Mapping (U2OCM1)
XHCI USB2 Overcurrent Pin Mapping (U2OCM2)
XHCI USB2 Overcurrent Pin Mapping (U2OCM3)
XHCI USB2 Overcurrent Pin Mapping (U2OCM4)
XHCI USB2 Overcurrent Pin Mapping (U2OCM5)
XHCI USB2 Overcurrent Pin Mapping (U2OCM6)
XHCI USB2 Overcurrent Pin Mapping (U2OCM7)
XHCI USB2 Overcurrent Pin Mapping (U2OCM8)
XHCI USB3 Overcurrent Pin Mapping (U3OCM1)
XHCI USB3 Overcurrent Pin Mapping (U3OCM2)
XHCI USB3 Overcurrent Pin Mapping (U3OCM3)
XHCI USB3 Overcurrent Pin Mapping (U3OCM4)
XHCI USB3 Overcurrent Pin Mapping (U3OCM5)
XHCI USB3 Overcurrent Pin Mapping (U3OCM6)
XHCI USB3 Overcurrent Pin Mapping (U3OCM7)
XHCI USB3 Overcurrent Pin Mapping (U3OCM8)
xHCI PCI Configuration (D20:F0)
Vendor ID (VID)
Device ID (DID)
Command Reg (CMD)
Device Status (STS)
Revision ID (RID)
Programming Interface (PI)
Sub Class Code (SCC)
Base Class Code (BCC)
Cache Line Size (CLS)
Master Latency Timer (MLT)
Header Type (HT)
Memory Base Address (MBAR)
USB Subsystem Vendor ID (SSVID)
USB Subsystem ID (SSID)
Capabilities Pointer (CAP_PTR)
Interrupt Line (ILINE)
Interrupt Pin (IPIN)
XHC System Bus Configuration 1 (XHCC1)
XHC System Bus Configuration 2 (XHCC2)
Clock Gating (XHCLKGTEN)
Audio Time Synchronization (AUDSYNC)
Serial Bus Release Number (SBRN)
Frame Length Adjustment (FLADJ)
Best Effort Service Latency (BESL)
PCI Power Management Capability ID (PM_CID)
Next Item Pointer 1 (PM_NEXT)
Power Management Capabilities (PM_CAP)
Power Management Control/Status (PM_CS)
Message Signaled Interrupt CID (MSI_CID)
Next Item Pointer (MSI_NEXT)
Message Signaled Interrupt Message Control (MSI_MCTL)
Message Signaled Interrupt Message Address (MSI_MAD)
Message Signaled Interrupt Upper Address (MSI_MUAD)
Message Signaled Interrupt Message Data (MSI_MD)
High Speed Configuration 2 (HSCFG2)
Host Software Pad Ownership (HOSTSW_OWN_GPPASPI0_0) – Offset 130
Refer to Register Field for detail
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:26 | 0h | RO | Reserved (RSVD_0) Reserved |
| 25 | 0h | RO | HostSW_Own (HOSTSW_OWN_spi0_clk_loopbk) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 24 | 0h | RO | HostSW_Own (HOSTSW_OWN_espi_clk_loopbk) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 23 | 0h | RO | HostSW_Own (HOSTSW_OWN_xxspi0_clk) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 22 | 0h | RO | HostSW_Own (HOSTSW_OWN_xxspi0_flash_1_cs_b) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 21 | 0h | RO | HostSW_Own (HOSTSW_OWN_xxspi0_flash_0_cs_b) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 20 | 0h | RO | HostSW_Own (HOSTSW_OWN_xxspi0_tpm_cs_b) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 19 | 0h | RO | HostSW_Own (HOSTSW_OWN_xxspi0_miso_io_1) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 18 | 0h | RO | HostSW_Own (HOSTSW_OWN_xxspi0_mosi_io_0) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 17 | 0h | RO | HostSW_Own (HOSTSW_OWN_xxspi0_io_3) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 16 | 0h | RO | HostSW_Own (HOSTSW_OWN_xxspi0_io_2) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 15 | 0h | RW | HostSW_Own (HOSTSW_OWN_xxgpp_a_15) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 14 | 0h | RW | HostSW_Own (HOSTSW_OWN_xxgpp_a_14) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 13 | 0h | RW | HostSW_Own (HOSTSW_OWN_xxgpp_a_13) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 12 | 0h | RW | HostSW_Own (HOSTSW_OWN_xxgpp_a_12) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 11 | 0h | RW | HostSW_Own (HOSTSW_OWN_xxgpp_a_11) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 10 | 0h | RW | HostSW_Own (HOSTSW_OWN_xxgpp_a_10) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 9 | 0h | RW | HostSW_Own (HOSTSW_OWN_xxgpp_a_9) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 8 | 0h | RW | HostSW_Own (HOSTSW_OWN_xxgpp_a_8) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 7 | 0h | RW | HostSW_Own (HOSTSW_OWN_xxgpp_a_7) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 6 | 0h | RW | HostSW_Own (HOSTSW_OWN_xxgpp_a_6) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 5 | 0h | RW | HostSW_Own (HOSTSW_OWN_xxgpp_a_5) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 4 | 0h | RW | HostSW_Own (HOSTSW_OWN_xxgpp_a_4) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 3 | 0h | RW | HostSW_Own (HOSTSW_OWN_xxgpp_a_3) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 2 | 0h | RW | HostSW_Own (HOSTSW_OWN_xxgpp_a_2) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 1 | 0h | RW | HostSW_Own (HOSTSW_OWN_xxgpp_a_1) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |
| 0 | 0h | RW | HostSW_Own (HOSTSW_OWN_xxgpp_a_0) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only. [/br] Bit assignment: Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= pad N-1 Note: N is the number of Pads in the Community. Optionally N may be the number of pads for a group of pads in the Community. In which case there is a register for each group. \t\t\t |