NPK Device Specific Control (NPKDSC) – Offset 80 - 001 - ID:831520 | Intel® Core™ Ultra 200V Series Processors SOC I/O Registers

Intel® Core™ Ultra 200V Series Processors SOC I/O Registers

ID	Date	Version	Classification
831520	09/03/2024	001	Public

NPK Device Specific Control (NPKDSC) – Offset 80

Bit Range	Default	Access	Field Name and Description
31:11	0h	RO	Reserved
10	0h	RW/1C	(URD) Unsupported Request Detect: This bit is set when an unsupported request is detected Unsupported Request Detect: This bit is set when an unsupported request is detected
9	0h	RW/1C	(CTOE) CCB Timeout Timer Expired: This bit is asserted if the Inbound CCB timeout timer has expired at least once CCB Timeout Timer Expired: This bit is asserted if the Inbound CCB timeout timer has expired at least once
8	0h	RW/1C	(STOE) Switch Timeout Timer Expired: This bit is asserted if the Inbound Switch timeout timer has expired at least once Switch Timeout Timer Expired: This bit is asserted if the Inbound Switch timeout timer has expired at least once
7	0h	RW	(ISACT) IOSF Sideband Active: Setting this bit will force North Peak to request its IOSF Sideband clock (ISBCLK) independent of any activity. This bit must be cleared before North Peak s Vnn domain can be power gated Sideband Bus Active: Setting this bit will force the Intel Trace Hub to request its Sideband bus clock (ISBCLK) independent of any activity.
6	0h	RW	(IPACT) IOSF Primary Active: Setting this bit will force North Peak to request its IOSF Primary clock (IPCLK) independent of any activity. This bit must be cleared before North Peak s Vnn domain can be power gated Primary Bus Active: Setting this bit will force the Intel Trace Hub to request its Primary bus clock (IPCLK) independent of any activity.
5	1h	RW	(TSACT) Time Stamping Active: Setting this bit will force North Peak to maintain requesting the XCLK and disable internal clock gating Time Stamping Active: Setting this bit will force the Intel Trace Hub to maintain requesting the time-stamping clock and disable internal clock gating
4	1h	RW	(TRACT) Tracing Active: Setting this bit will force North Peak to request its North Peak clock (NPCLK) independent of any activity and disable clock gating Tracing Active: Setting this bit will force the Intel Trace Hub to request its NPCLK clock. This effectively disables clock gating
3	0h	RW	(URRE) Unsupported Request Reporting Enable: When set, this bit enables the reporting unsupported requests as system errors Unsupported Request Reporting Enable: When set, this bit enables the reporting unsupported requests as system errors
2	0h	RW/1C	(CDINTS) Capture Done Interrupt Status: Formerly Legacy Interrupt Asserted. Equivalent to MSUSTS.MSU_INT. For software compatibility, this this bit indicates when the capture done event has occurred. Software can clear the capture done interrupt event by writing a 1 to this bit, or writing a 1 to the MSUSTS.MSU_INT bit
1	0h	RW	(FLR) Software Reset: Writing a 1 to this bit will assert the reset signals. Reading this bit will always return a zero.
0	0h	RSV	(RSVD) Reserved Reserved. Software must ignore these bits on reads, and must write zeroes to these bits on writes.