Configuration Flow

Legal Disclaimer
Revision History
Introduction
PCH Controller Device IDs
- Revision IDs
- Device IDs
Memory Mapping
- Functional Description
- Memory Map
Audio Voice and Speech
Ballout Definition
Connectivity Integrated (CNVi)
Controller Link
Direct Enhanced Serial Peripheral Interface (Direct eSPI)
Direct Media Interface (DMI)
Enhanced Serial Peripheral Interface (eSPI)
Gigabit Ethernet Controller
Host System Management Bus (SMBus) Controller
Integrated Sensor Hub (ISH)
Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Intel® Serial IO Generic SPI (GSPI) Controllers
PCI Express* (PCIe*)
Real Time Clock (RTC)
- Signal Description
- I/O Signal Planes and States
Serial ATA (SATA)
Serial Peripheral Interface (SPI)
System Clocks
- Integrated Clock Controller (ICC)
  - Signal Descriptions
- I/O Signal Pin States
System Management Interface and SMLink
Touch Host Controller (THC)
Universal Serial Bus (USB)
General Purpose Input and Output
- Functional Description
- Signal Description
GPIO Serial Expander
Private Configuration Space Port ID
Security Firmware Engines
- Intel® Converged Security and Management Engine (Intel® CSME)
- Intel® Silicon Security Engine
System Management
- Theory of Operation
  - TCO Modes
Testability and Monitoring
- Signal Description
- I/O Signal Planes and States
Miscellaneous Signals
Processor Sideband Signals
- Signal Description
- I/O Signal Planes and States
Power Delivery
- Power and Ground Signals
Power Management
Thermal Sensor
Electrical Characteristics

The processor's present pin strap is tied with the PCH eSPI enable strap pin during the platform configuration flow. Depending on the processor's present pin strap status and PCH eSPI enable pin strap status, the PCH Direct eSPI target takes the decision to configure the flash, VW, and peripheral channel.

In an instance when an EC is attached to the PCH eSPI controller, the PCH Direct eSPI target waits if the PCH eSPI controller's flash, VW, and the peripheral channel are ready before it can set the ready bit of the respective channel on Direct eSPI interface.

The PCH Direct eSPI target configures the channel depending on the GET_CONFIG/SET_CONFIG/GET_STATUS/INBAND Reset commands and the latest channel/link capability information (e.g. flash, RPMC eSPI capability or SPI flash SFDP), which were gathered from its downstream PCH eSPI EC/other devices or SPI controller.

PCH Direct eSPI Registers

Functional Description PCH Direct eSPI Registers