Intel® 800 Series Chipset Family Platform Controller Hub (PCH)

Datasheet, Volume 1 of 2

ID Date Version Classification
833778 02/06/2025 Public
Document Table of Contents
Document Table of Contents
Legal Disclaimer Revision History Introduction PCH Controller Device IDs Memory Mapping Audio Voice and Speech Ballout Definition Connectivity Integrated (CNVi) Controller Link Direct Enhanced Serial Peripheral Interface (Direct eSPI) Direct Media Interface (DMI) Enhanced Serial Peripheral Interface (eSPI) Gigabit Ethernet Controller Host System Management Bus (SMBus) Controller Integrated Sensor Hub (ISH) Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers Intel® Serial IO Generic SPI (GSPI) Controllers PCI Express* (PCIe*) Real Time Clock (RTC) Serial ATA (SATA) Serial Peripheral Interface (SPI) System Clocks System Management Interface and SMLink Touch Host Controller (THC) Universal Serial Bus (USB) General Purpose Input and Output GPIO Serial Expander Private Configuration Space Port ID Security Firmware Engines System Management Testability and Monitoring Miscellaneous Signals Processor Sideband Signals Power Delivery Power Management Thermal Sensor Electrical Characteristics
Legal Disclaimer
Revision History
Introduction
Introduction Overview SKU Definition Flexible High Speed I/O
Overview
Overview Terminology and Special Marks
Terminology and Special Marks
SKU Definition
Flexible High Speed I/O
PCH Controller Device IDs
PCH Controller Device IDs Revision IDs Device IDs
Revision IDs
Device IDs
Memory Mapping
Memory Mapping Functional Description Memory Map
Functional Description
PCI Devices and Functions Fixed I/O Address Ranges Variable I/O Decode Ranges
PCI Devices and Functions
Fixed I/O Address Ranges
Variable I/O Decode Ranges
Memory Map
Audio Voice and Speech
Audio Voice and Speech Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities Audio DSP Capabilities Intel® High Definition Audio Interface Capabilities Direct Attached Digital Microphone (PDM) Interface USB Audio Offload Support I2S / PCM Interface Intel® Display Audio Interface MIPI® SoundWire* Interface Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
I2S / PCM Interface
Intel® Display Audio Interface
MIPI® SoundWire* Interface
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Ballout Definition
Connectivity Integrated (CNVi)
Connectivity Integrated (CNVi) Functional Description Signal Description Integrated Pull-ups and Pull-downs I/O Signal Planes and States
Functional Description
Signal Description
Integrated Pull-ups and Pull-downs
I/O Signal Planes and States
Controller Link
Controller Link Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States External CL_RST# Pin Driven/Open-drained Mode Support Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
External CL_RST# Pin Driven/Open-drained Mode Support
Signal Description
Direct Enhanced Serial Peripheral Interface (Direct eSPI)
Direct Enhanced Serial Peripheral Interface (Direct eSPI) Functional Description Protocols Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Configuration Flow PCH Direct eSPI Registers PCH Direct eSPI Reset Handling PCH Direct eSPI Peripheral Channel Support PCH Direct eSPI VW Channel Support PCH Direct eSPI OOB Channel Support PCH Direct eSPI Flash Channel Support PCH eSPI Switch Flash Descriptor Address Swapping
Configuration Flow
PCH Direct eSPI Registers
PCH Direct eSPI Reset Handling
PCH Direct eSPI Peripheral Channel Support
PCH Direct eSPI VW Channel Support
PCH Direct eSPI OOB Channel Support
PCH Direct eSPI Flash Channel Support
PCH eSPI Switch
Flash Descriptor Address Swapping
Protocols
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Direct Media Interface (DMI)
Direct Media Interface (DMI) Functional Description Signal Description I/O Signal Planes and States DMI Configuration DMI CLKREQ, DMI REFCLK, DMI PERST#
Functional Description
Functional Description Lane Reversal Polarity Inversion
Lane Reversal
Polarity Inversion
Signal Description
I/O Signal Planes and States
DMI Configuration
DMI CLKREQ, DMI REFCLK, DMI PERST#
Enhanced Serial Peripheral Interface (eSPI)
Enhanced Serial Peripheral Interface (eSPI) Functional Description Protocols Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Operating Frequency WAIT States from eSPI device In-Band Link Reset Flash Sharing Mode PECI Over eSPI Multiple OOB processes Channels and Supported Transactions
Operating Frequency
WAIT States from eSPI device
In-Band Link Reset
Flash Sharing Mode
PECI Over eSPI
Multiple OOB processes
Channels and Supported Transactions
Protocols
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Gigabit Ethernet Controller
Gigabit Ethernet Controller Signal Description Integrated Pull-Ups and Pull-Downs Functional Description
Signal Description
Integrated Pull-Ups and Pull-Downs
Functional Description
Functional Description GbE PCI Bus Interface Error Events and Error Reporting Ethernet Interface PCI Power Management
GbE PCI Bus Interface
Error Events and Error Reporting
Ethernet Interface
PCI Power Management
Host System Management Bus (SMBus) Controller
Host System Management Bus (SMBus) Controller Functional Description SMBus Power Gating Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Host Controller SMBus Target Interface
Host Controller
SMBus Target Interface
SMBus Power Gating
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Integrated Sensor Hub (ISH)
Integrated Sensor Hub (ISH) Features Functional Description Signal Description Integrated Pull-Ups and Pull-Down I/O Signal Planes and States
Features
ISH I2C Controllers ISH GSPI Controller ISH UART Controller ISH GPIOs
ISH I2C Controllers
ISH GSPI Controller
ISH UART Controller
ISH GPIOs
Functional Description
Functional Description ISH Micro-Controller SRAM PCI Host Interface ISH IPC ISH Interrupt Handling via IOAPIC (Interrupt Controller)
ISH Micro-Controller
SRAM
PCI Host Interface
ISH IPC
ISH Interrupt Handling via IOAPIC (Interrupt Controller)
Signal Description
Integrated Pull-Ups and Pull-Down
I/O Signal Planes and States
Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers
Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Reset Power Management Interrupts
Reset
Power Management
Interrupts
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Protocols Overview DMA Controller Reset Power Management Interrupts Error Handling Programmable SDA Hold Time
Protocols Overview
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Programmable SDA Hold Time
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
UART Serial (RS-232) Protocols Overview 16550 8-bit Addressing - Debug Driver Compatibility DMA Controller Reset Power Management Interrupts Error Handling
UART Serial (RS-232) Protocols Overview
16550 8-bit Addressing - Debug Driver Compatibility
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Intel® Serial IO Generic SPI (GSPI) Controllers
Intel® Serial IO Generic SPI (GSPI) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Controller Overview DMA Controller Reset Power Management Interrupts Error Handling
Controller Overview
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
PCI Express* (PCIe*)
PCI Express* (PCIe*) Functional Description Signal Description I/O Signal Planes and States PCI Express* Root Port Support Feature Details
Functional Description
Functional Description PCI Express* Power Management Port 80h Decode Advanced Error Reporting Single - Root I/O Virtualization (SR - IOV) PCI Express* Receiver Lane Polarity Inversion Precision Time Measurement (PTM)
PCI Express* Power Management
Port 80h Decode
Advanced Error Reporting
Single - Root I/O Virtualization (SR - IOV)
PCI Express* Receiver Lane Polarity Inversion
Precision Time Measurement (PTM)
Signal Description
I/O Signal Planes and States
PCI Express* Root Port Support Feature Details
Real Time Clock (RTC)
Real Time Clock (RTC) Signal Description I/O Signal Planes and States
Signal Description
I/O Signal Planes and States
Serial ATA (SATA)
Serial ATA (SATA) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Features Supported SATA 6 Gb/s Support Hot Plug Operation Intel® Rapid Storage Technology (Intel® RST) Power Management Operation SATA Device Presence SATA LED Advanced Host Controller Interface (AHCI) Operation Enclosure Management (SGPIO Signals)
Features Supported
SATA 6 Gb/s Support
Hot Plug Operation
Intel® Rapid Storage Technology (Intel® RST)
Power Management Operation
SATA Device Presence
SATA LED
Advanced Host Controller Interface (AHCI) Operation
Enclosure Management (SGPIO Signals)
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
SPI0 for Flash SPI0 Support for TPM
SPI0 for Flash
SPI0 Support for TPM
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
System Clocks
System Clocks Integrated Clock Controller (ICC) I/O Signal Pin States
Integrated Clock Controller (ICC)
Integrated Clock Controller (ICC) Signal Descriptions
Signal Descriptions
I/O Signal Pin States
System Management Interface and SMLink
System Management Interface and SMLink Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Integrated USB-C* Usage
Integrated USB-C* Usage
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Touch Host Controller (THC)
Touch Host Controller (THC) Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Functional Description
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Universal Serial Bus (USB)
Universal Serial Bus (USB) Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States Supported USB 2.0 Ports Functional Description
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Supported USB 2.0 Ports
Functional Description
eXtensible Host Controller Interface (xHCI) Controller USB Dual Role Support - eXtensible Device Controller Interface (xDCI) Controller
eXtensible Host Controller Interface (xHCI) Controller
USB Dual Role Support - eXtensible Device Controller Interface (xDCI) Controller
General Purpose Input and Output
General Purpose Input and Output Functional Description Signal Description
Functional Description
Functional Description Configurable GPIO Voltage Interrupt / IRQ via GPIO Requirement Integrated Pull-ups and Pull-downs SCI / SMI and NMI GPIO Blink (BK) and Serial Blink (SBK) GPIO Ownership Native Function and TERM Bit Setting
Configurable GPIO Voltage
Interrupt / IRQ via GPIO Requirement
Integrated Pull-ups and Pull-downs
SCI / SMI and NMI
GPIO Blink (BK) and Serial Blink (SBK)
GPIO Ownership
Native Function and TERM Bit Setting
Signal Description
GPIO Serial Expander
GPIO Serial Expander Signal Description Integrated Pull-ups and Pull-downs Functional Description
Signal Description
Integrated Pull-ups and Pull-downs
Functional Description
Private Configuration Space Port ID
Security Firmware Engines
Intel® Converged Security and Management Engine (Intel® CSME) Intel® Silicon Security Engine
Intel® Converged Security and Management Engine (Intel® CSME)
Intel® Silicon Security Engine
System Management
System Management Theory of Operation
Theory of Operation
Theory of Operation TCO Modes
TCO Modes
Testability and Monitoring
Testability and Monitoring Signal Description I/O Signal Planes and States
Signal Description
I/O Signal Planes and States
Miscellaneous Signals
Signal Description Integrated Pull-Ups and Pull-Downs Ground and Reserved Signals
Signal Description
Integrated Pull-Ups and Pull-Downs
Ground and Reserved Signals
Processor Sideband Signals
Processor Sideband Signals Signal Description I/O Signal Planes and States
Signal Description
I/O Signal Planes and States
Power Delivery
Power and Ground Signals
Power and Ground Signals
Power Management
Power Management System Power States, Advanced Configuration and Power Interface (ACPI) Legacy Power Management Support Functional Description Power and Internal Signals
System Power States, Advanced Configuration and Power Interface (ACPI)
Legacy Power Management Support
Legacy Power Management Support ALT Access Mode Legacy Power Management Theory of Operation
ALT Access Mode
Legacy Power Management Theory of Operation
Functional Description
Functional Description Features Power Saving Features SMI#/SCI Generation Sleep States Event Input Signals and Their Usage System Power Supplies, Planes, and Signals Reset Behavior Legacy Power Management Theory of Operation
Features
Power Saving Features
SMI#/SCI Generation
Sleep States
Event Input Signals and Their Usage
System Power Supplies, Planes, and Signals
Reset Behavior
Legacy Power Management Theory of Operation
Power and Internal Signals
Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Thermal Sensor
Thermal Sensor Modes of Operation Temperature Trip Point Thermal Sensor Accuracy (Taccuracy) Thermal Reporting to EC Thermal Trip Signal (PCHHOT#)
Modes of Operation
Temperature Trip Point
Thermal Sensor Accuracy (Taccuracy)
Thermal Reporting to EC
Thermal Trip Signal (PCHHOT#)
Electrical Characteristics

Features Supported

The SATA controller is capable of supporting all AHCI 1.3 and AHCI 1.3.1. Refer to the Intel web site on Advanced Host Controller Interface Specification for current specification status: http://www.intel.com/content/www/us/en/io/serial-ata/ahci.html.

For capability details, refer to SATA controller register .

The SATA supports the following features:

  • Port Multiplier:
    • The SATA controller may optionally support command-based switching Port Multipliers. Note:BIOS must clear this bit if Port Multipliers are not supported.
  • Host Initiated Loopback Mode:
    • The need to use PxCMD.CLO to clear the internal BSY bit before setting the PxCMD.ST to '1', as there is no power-up register FIS from device to clear the BSY bit.
    • Only one CI bit can be set per each Loopback session.
    • Only one PRD can be used in each CI.
    • Only PRD size of 256B is supported.
    • Only CL.CFL=0 is supported
    • Need to set the CL.P bit for the CI, to allow PRD prefetch, without waiting for device FIS.
    • Need to clear the PxCMD.ST bit after the loopback session done and set it again to start another session.

The SATA controller does not support:

  • FIS Based Switching
  • IDE mode or combination mode
  • Cold Presence Detect
SATA 6 Gb/s Support