Intel® 800 Series Chipset Family Platform Controller Hub (PCH)
Datasheet, Volume 1 of 2
| ID | Date | Version | Classification |
|---|---|---|---|
| 833778 | 02/06/2025 | Public |
Legal Disclaimer
Revision History
Introduction
PCH Controller Device IDs
Memory Mapping
Audio Voice and Speech
Ballout Definition
Connectivity Integrated (CNVi)
Controller Link
Direct Enhanced Serial Peripheral Interface (Direct eSPI)
Direct Media Interface (DMI)
Enhanced Serial Peripheral Interface (eSPI)
Gigabit Ethernet Controller
Host System Management Bus (SMBus) Controller
Integrated Sensor Hub (ISH)
Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Intel® Serial IO Generic SPI (GSPI) Controllers
PCI Express* (PCIe*)
Real Time Clock (RTC)
Serial ATA (SATA)
Serial Peripheral Interface (SPI)
System Clocks
System Management Interface and SMLink
Touch Host Controller (THC)
Universal Serial Bus (USB)
General Purpose Input and Output
GPIO Serial Expander
Private Configuration Space Port ID
Security Firmware Engines
System Management
Testability and Monitoring
Miscellaneous Signals
Processor Sideband Signals
Power Delivery
Power Management
Thermal Sensor
Electrical Characteristics
Audio Voice and Speech
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
I2S / PCM Interface
Intel® Display Audio Interface
MIPI® SoundWire* Interface
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Functional Description
Configuration Flow
PCH Direct eSPI Registers
PCH Direct eSPI Reset Handling
PCH Direct eSPI Peripheral Channel Support
PCH Direct eSPI VW Channel Support
PCH Direct eSPI OOB Channel Support
PCH Direct eSPI Flash Channel Support
PCH eSPI Switch
Flash Descriptor Address Swapping
Signal Description
| Signal Name | Type | Description |
|---|---|---|
| DMI0_TXP DMI0_TXN | O | DMI transmit lane 0 |
| DMI0_RXP DMI0_RXN | I | DMI receive lane 0 |
| DMI1_TXP DMI1_TXN | O | DMI transmit lane 1 |
| DMI1_RXP DMI1_RXN | I | DMI receive lane 1 |
| DMI2_TXP DMI2_TXN | O | DMI transmit lane 2 |
| DMI2_RXP DMI2_RXN | I | DMI receive lane 2 |
| DMI3_TXP DMI3_TXN | O | DMI transmit lane 3 |
| DMI3_RXP DMI3_RXN | I | DMI receive lane 3 |
| DMI4_TXP DMI4_TXN | O | DMI transmit lane 4 |
| DMI4_RXP DMI4_RXN | I | DMI receive lane 4 |
| DMI5_TXP DMI5_TXN | O | DMI transmit lane 5 |
| DMI5_RXP DMI5_RXN | I | DMI receive lane 5 |
| DMI6_TXP DMI6_TXN | O | DMI transmit lane 6 |
| DMI6_RXP DMI6_RXN | I | DMI receive lane 6 |
| DMI7_TXP DMI7_TXN | O | DMI transmit lane 7 |
| DMI7_RXP DMI7_RXN | I | DMI receive lane 7 |
| DMI_PERST# | I | DMI PERST Strobe |
| DMI_RCOMP | I | DMI Impedance Compensation Inputs |